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gatemate_experiments
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209 KiB
VHDL
71.6%
Makefile
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Verilog
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C
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Tcl
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gatemate_experiments
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uart
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T. Meissner
1003634110
Add inital version of uart register test design
2 years ago
..
rtl
Add inital version of uart register test design
2 years ago
syn
Add inital version of uart register test design
2 years ago