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73 lines
1.6 KiB
73 lines
1.6 KiB
library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.env.all;
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entity tb_neorv32_aes is
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end entity tb_neorv32_aes;
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architecture sim of tb_neorv32_aes is
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constant c_baudrate : natural := 9600;
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constant c_period_ns : time := 1000000000 / c_baudrate * ns;
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procedure uart_send ( data : in std_logic_vector(7 downto 0);
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signal tx : out std_logic) is
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begin
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report "UART send: 0x" & to_hstring(data);
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tx <= '0';
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wait for c_period_ns;
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for i in 0 to 7 loop
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tx <= data(i);
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wait for c_period_ns;
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end loop;
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tx <= '1';
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wait for c_period_ns;
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end procedure;
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procedure uart_recv ( data : out std_logic_vector(7 downto 0);
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signal rx : in std_logic) is
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begin
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wait until not rx;
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wait for c_period_ns; -- Skip start bit
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wait for c_period_ns/2;
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for i in 0 to 7 loop
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data(i) := rx;
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wait for c_period_ns;
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end loop;
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report "UART recv: 0x" & to_hstring(data);
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end procedure;
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signal s_clk : std_logic := '1';
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signal s_rst_n : std_logic := '0';
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signal s_len_n : std_logic_vector(7 downto 0);
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signal s_debug : std_logic_vector(15 downto 0);
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begin
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dut : entity work.neorv32_aes
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port map (
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clk_i => s_clk,
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rst_n_i => s_rst_n,
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--
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led_n_o => s_len_n,
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--uart_tx_o => s_uart_tx
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--uart_rx_i => s_uart_rx
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debug_o => s_debug
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);
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s_rst_n <= '1' after 120 ns;
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s_clk <= not s_clk after 50 ns;
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process is
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begin
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wait for 2 ms;
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stop(0);
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end process;
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end architecture;
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