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125 lines
3.5 KiB
125 lines
3.5 KiB
library ieee ;
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use ieee.std_logic_1164.all;
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package uart_aes_sim is
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generic (
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period_ns : time
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);
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procedure uart_send ( data : in std_logic_vector(7 downto 0);
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signal tx : out std_logic);
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procedure uart_recv ( data : out std_logic_vector(7 downto 0);
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signal rx : in std_logic);
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procedure aes_setup ( key : in std_logic_vector(0 to 127);
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nonce : in std_logic_vector(0 to 95);
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signal tx : out std_logic);
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procedure aes_write ( data : in std_logic_vector(0 to 127);
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signal tx : out std_logic);
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procedure aes_read ( data : out std_logic_vector(0 to 127);
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signal tx : out std_logic;
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signal rx : in std_logic);
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procedure aes_crypt (signal tx : out std_logic;
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signal rx : in std_logic);
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end package;
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package body uart_aes_sim is
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procedure uart_send ( data : in std_logic_vector(7 downto 0);
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signal tx : out std_logic) is
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begin
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report "UART send: 0x" & to_hstring(data);
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wait for period_ns;
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tx <= '0';
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wait for period_ns;
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for i in 0 to 7 loop
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tx <= data(i);
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wait for period_ns;
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end loop;
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tx <= '1';
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wait for 0 ns;
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end procedure;
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procedure uart_recv ( data : out std_logic_vector(7 downto 0);
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signal rx : in std_logic) is
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begin
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wait until not rx;
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wait for period_ns; -- Skip start bit
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wait for period_ns/2;
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for i in 0 to 7 loop
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data(i) := rx;
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wait for period_ns;
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end loop;
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report "UART recv: 0x" & to_hstring(data);
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end procedure;
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procedure aes_setup ( key : in std_logic_vector(0 to 127);
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nonce : in std_logic_vector(0 to 95);
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signal tx : out std_logic) is
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begin
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-- Reset control register
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uart_send(x"01", tx);
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uart_send(x"01", tx);
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-- Write key register
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for i in 0 to 15 loop
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uart_send(x"11", tx);
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uart_send(key(i*8 to i*8+7), tx);
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end loop;
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-- Write nonce register
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for i in 0 to 11 loop
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uart_send(x"21", tx);
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uart_send(nonce(i*8 to i*8+7), tx);
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end loop;
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-- Set control registers CTR_START bit
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uart_send(x"01", tx);
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uart_send(x"02", tx);
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end procedure;
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procedure aes_write ( data : in std_logic_vector(0 to 127);
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signal tx : out std_logic) is
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begin
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-- Write din register
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for i in 0 to 15 loop
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uart_send(x"31", tx);
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uart_send(data(i*8 to i*8+7), tx);
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end loop;
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end procedure;
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procedure aes_read ( data : out std_logic_vector(0 to 127);
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signal tx : out std_logic;
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signal rx : in std_logic) is
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variable v_data : std_logic_vector(7 downto 0);
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begin
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-- Check for valid AES output data
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loop
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uart_send(x"00", tx);
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uart_recv(v_data, rx);
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exit when v_data(3);
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end loop;
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-- Read dout register
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for i in 0 to 15 loop
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uart_send(x"40", tx);
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uart_recv(data(i*8 to i*8+7), rx);
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end loop;
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end procedure;
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procedure aes_crypt (signal tx : out std_logic;
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signal rx : in std_logic) is
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variable v_data : std_logic_vector(7 downto 0);
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begin
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uart_send(x"00", tx);
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uart_recv(v_data, rx);
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v_data(2) := '1';
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-- Set control registers CTR_START bit
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uart_send(x"01", tx);
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uart_send(v_data, tx);
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end procedure;
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end package body;
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