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105 lines
2.8 KiB
105 lines
2.8 KiB
-- Copyright (c) 2022 by Torsten Meissner
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- https://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity uart_rx is
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generic (
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CLK_DIV : natural := 10
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);
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port (
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-- globals
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rst_n_i : in std_logic;
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clk_i : in std_logic;
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-- axis user interface
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tdata_o : out std_logic_vector(7 downto 0);
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tvalid_o : out std_logic;
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tready_i : in std_logic;
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-- uart interface
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rx_i : in std_logic
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);
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end entity uart_rx;
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architecture rtl of uart_rx is
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type t_uart_state is (IDLE, RECEIVE, VALID);
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signal s_uart_state : t_uart_state;
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signal s_clk_en : std_logic;
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signal s_clk_cnt : natural range 0 to CLK_DIV-1;
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signal s_bit_cnt : natural range 0 to tdata_o'length+1;
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signal s_rx_d : std_logic_vector(3 downto 0);
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begin
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ClkDivP : process (clk_i, rst_n_i) is
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begin
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if (not rst_n_i) then
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s_clk_cnt <= CLK_DIV-1;
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elsif (rising_edge(clk_i)) then
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if (s_uart_state = IDLE) then
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s_clk_cnt <= CLK_DIV-2;
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elsif (s_uart_state = RECEIVE) then
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if (s_clk_cnt = 0) then
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s_clk_cnt <= CLK_DIV-1;
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else
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s_clk_cnt <= s_clk_cnt - 1;
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end if;
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end if;
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end if;
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end process ClkDivP;
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s_clk_en <= '1' when s_uart_state = RECEIVE and s_clk_cnt = CLK_DIV/2-1 else '0';
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RxP : process (clk_i, rst_n_i) is
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begin
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if (not rst_n_i) then
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s_uart_state <= IDLE;
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tdata_o <= (others => '0');
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s_rx_d <= x"1";
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s_bit_cnt <= 0;
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elsif (rising_edge(clk_i)) then
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s_rx_d <= s_rx_d(2 downto 0) & rx_i;
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FsmL : case s_uart_state is
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when IDLE =>
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s_bit_cnt <= tdata_o'length+1;
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if (s_rx_d = "1000") then
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s_uart_state <= RECEIVE;
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end if;
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when RECEIVE =>
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if (s_clk_en) then
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if (s_bit_cnt = 0) then
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s_uart_state <= VALID;
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else
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tdata_o <= s_rx_d(3) & tdata_o(tdata_o'length-1 downto 1);
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s_bit_cnt <= s_bit_cnt - 1;
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end if;
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end if;
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when VALID =>
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if (tready_i) then
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s_uart_state <= IDLE;
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end if;
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end case;
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end if;
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end process RxP;
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tvalid_o <= '1' when s_uart_state = VALID else '0';
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end architecture rtl;
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