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137 lines
3.0 KiB
137 lines
3.0 KiB
-- This design implements a register file which can
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-- be accessed by an UART with 9600 baud
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--
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-- See into uart_ctrl.vhd for documentation of the protocol
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-- used to read / write the register file.
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library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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library gatemate;
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use gatemate.components.all;
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entity uart_trng is
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generic (
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SIM : natural := 0
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);
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port (
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clk_i : in std_logic; -- 10 MHz clock
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rst_n_i : in std_logic; -- SW3 button
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uart_tx_o : out std_logic -- PMODA IO5
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);
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end entity uart_trng;
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architecture rtl of uart_trng is
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signal s_pll_clk : std_logic;
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signal s_pll_lock : std_logic;
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signal s_rst_n : std_logic;
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signal s_cfg_end : std_logic;
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signal s_uart_tx_tdata : std_logic_vector(7 downto 0);
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signal s_uart_tx_tvalid : std_logic;
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signal s_uart_tx_tready : std_logic;
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signal s_firo_run : std_logic;
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signal s_firo_data : std_logic;
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begin
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pll : CC_PLL
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generic map (
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REF_CLK => "10",
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OUT_CLK => "10",
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PERF_MD => "ECONOMY"
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)
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port map (
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CLK_REF => clk_i,
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CLK_FEEDBACK => '0',
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USR_CLK_REF => '0',
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USR_LOCKED_STDY_RST => '0',
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USR_PLL_LOCKED_STDY => open,
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USR_PLL_LOCKED => s_pll_lock,
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CLK270 => open,
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CLK180 => open,
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CLK0 => s_pll_clk,
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CLK90 => open,
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CLK_REF_OUT => open
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);
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cfg_end_inst : CC_CFG_END
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port map (
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CFG_END => s_cfg_end
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);
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firo_ctrl : entity work.firo_ctrl
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generic map (
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EXTRACT => true
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)
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port map (
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-- system
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rst_n_i => s_rst_n,
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clk_i => s_pll_clk,
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-- axis in
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tvalid_i => '1',
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tready_o => open,
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-- axis out
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tdata_o => s_uart_tx_tdata,
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tvalid_o => s_uart_tx_tvalid,
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tready_i => s_uart_tx_tready,
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-- firo
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frun_o => s_firo_run,
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fdata_i => s_firo_data
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);
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SIMULATION : if (SIM /= 0) generate
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-- simple random bit generator
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RandomGenP : process (s_pll_clk, s_firo_run) is
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variable v_seed1, v_seed2 : positive := 1;
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variable v_real_rand : real;
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begin
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if (not s_firo_run) then
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s_firo_data <= '0';
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elsif (s_pll_clk'event) then
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uniform(v_seed1, v_seed2, v_real_rand);
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if (v_real_rand < 0.5) then
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s_firo_data <= '0';
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else
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s_firo_data <= '1';
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end if;
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end if;
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end process RandomGenP;
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else generate
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firo : entity work.firo
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generic map (
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TOGGLE => true
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)
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port map (
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frun_i => s_firo_run,
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fdata_o => s_firo_data
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);
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end generate;
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uart_tx : entity work.uart_tx
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generic map (
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CLK_DIV => 1040
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)
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port map (
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-- globals
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rst_n_i => s_rst_n,
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clk_i => s_pll_clk,
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-- axis user interface
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tdata_i => s_uart_tx_tdata,
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tvalid_i => s_uart_tx_tvalid,
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tready_o => s_uart_tx_tready,
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-- uart interface
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tx_o => uart_tx_o
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);
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s_rst_n <= rst_n_i and s_pll_lock and s_cfg_end;
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end architecture;
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