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30 lines
896 B
30 lines
896 B
DESIGN_NAME := uart_loop
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LIB_SRC := ../../lib/rtl_components.vhd ../../lib/sim_components.vhd
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RTL_SRC := ../../lib/user_components.vhd ../rtl/uart_tx.vhd ../rtl/uart_rx.vhd ../rtl/${DESIGN_NAME}.vhd
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SIM_SRC := tb_${DESIGN_NAME}.vhd
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SIM_FLAGS := --std=08 -fpsl --workdir=work
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.PHONY: all compile sim clean
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all: sim
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compile: tb_${DESIGN_NAME}
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tb_${DESIGN_NAME}: ${LIB_SRC} ${RTL_SRC} ${SIM_SRC}
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mkdir -p work
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@echo "Analyze gatemate library ..."
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ghdl -a ${SIM_FLAGS} --work=gatemate ${LIB_SRC}
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@echo "Analyze testbench & design ..."
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ghdl -a ${SIM_FLAGS} -Pwork ${RTL_SRC} ${SIM_SRC}
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@echo "Elaborate testbench & design ..."
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ghdl -e ${SIM_FLAGS} -Pwork $@
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sim: tb_${DESIGN_NAME}
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@echo "Run testbench ..."
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ghdl -r ${SIM_FLAGS} -Pwork tb_${DESIGN_NAME} --assert-level=error
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work:
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mkdir $@
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clean:
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@echo "Cleaning simulation files ..."
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rm -rf tb_${DESIGN_NAME} *.o work/
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