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119 lines
5.4 KiB
119 lines
5.4 KiB
-- #################################################################################################
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-- # << NEORV32 - Example setup including the bootloader, for the Gatemate (c) Eval Board >> #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2022, Torsten Meissner. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library gatemate;
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use gatemate.components.all;
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entity neorv32_aes is
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port (
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-- Clock and Reset inputs
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clk_i : in std_logic; -- 10 MHz clock
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rst_n_i : in std_logic; -- SW3 button
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-- LED outputs
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led_n_o : out std_logic_vector(7 downto 0);
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-- UART0
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uart_rx_i : in std_logic; -- PMODA IO
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uart_tx_o : out std_logic -- PMODA IO
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);
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end entity;
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architecture rtl of neorv32_aes is
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-- configuration --
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constant f_clock_c : natural := 26_000_000; -- clock frequency in Hz
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-- Globals
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signal s_pll_lock : std_logic;
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signal s_pll_clk : std_logic;
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signal s_cfg_end : std_logic;
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signal s_rst_n : std_logic;
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signal s_con_pwm : std_logic_vector(2 downto 0);
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begin
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PLL : CC_PLL
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generic map (
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REF_CLK => "10",
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OUT_CLK => "26",
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PERF_MD => "SPEED"
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)
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port map (
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CLK_REF => clk_i,
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USR_CLK_REF => '0',
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CLK_FEEDBACK => '0',
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USR_LOCKED_STDY_RST => '0',
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USR_PLL_LOCKED_STDY => open,
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USR_PLL_LOCKED => s_pll_lock,
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CLK0 => s_pll_clk,
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CLK90 => open,
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CLK180 => open,
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CLK270 => open,
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CLK_REF_OUT => open
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);
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cfg_end : CC_CFG_END
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port map (
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CFG_END => s_cfg_end
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);
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s_rst_n <= s_pll_lock and s_cfg_end and rst_n_i;
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-- The core of the problem ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_inst: entity work.neorv32_ProcessorTop_Minimal
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generic map (
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CLOCK_FREQUENCY => f_clock_c -- clock frequency of s_pll_clk in Hz
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)
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port map (
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-- Global control --
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clk_i => std_ulogic(s_pll_clk),
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rstn_i => std_ulogic(s_rst_n),
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-- PWM (to on-board RGB LED) --
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pwm_o => s_con_pwm
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);
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-- IO Connection --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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led_n_o(4 downto 0) <= (others => '1');
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led_n_o(7 downto 5) <= s_con_pwm;
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uart_tx_o <= uart_rx_i;
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end architecture;
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