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18 Commits
2 Branches
209 KiB
VHDL 71.6%
Makefile 13.9%
Verilog 8.7%
C 5.4%
Tcl 0.4%
 
 
 
 
 
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gatemate_experiments/uart_reg/sim
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T. Meissner 61affc8b49 Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations 2 years ago
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Makefile Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations 2 years ago
tb_uart_reg.vhd Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations 2 years ago
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