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51 lines
1.9 KiB
51 lines
1.9 KiB
DESIGN_NAME := uart_loop
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WORK_FILES := ../../lib/user_components.vhd ../rtl/uart_tx.vhd ../rtl/uart_rx.vhd ../rtl/${DESIGN_NAME}.vhd
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GM_FILES := ../../lib/rtl_components.vhd
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GHDL_FLAGS := --std=08 --workdir=build -Pbuild
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YOSYSPIPE := -nomx8 -retime
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# ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate?
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PNRFLAGS := -om 3
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PNRTOOL := $(shell which p_r)
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.PHONY: all syn imp prog syn_sim imp_sim
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all: imp
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syn: ${DESIGN_NAME}.v
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imp: ${DESIGN_NAME}.bit
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build/work-obj08.cf: ${WORK_FILES} build/gatemate-obj08.cf
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ghdl -a ${GHDL_FLAGS} --work=work ${WORK_FILES}
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build/gatemate-obj08.cf: ${GM_FILES}
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mkdir -p build
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ghdl -a ${GHDL_FLAGS} --work=gatemate ${GM_FILES}
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# Synthesis target for implementation
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${DESIGN_NAME}.v: build/work-obj08.cf
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yosys -m ghdl -p 'ghdl ${GHDL_FLAGS} --warn-no-binding --no-formal ${DESIGN_NAME}; synth_gatemate -top $(DESIGN_NAME) ${YOSYSPIPE} -vlog $@' \
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2>&1 | tee build/yosys-report.txt
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# Implementation target for FPGA
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${DESIGN_NAME}.bit: ${DESIGN_NAME}.v ${DESIGN_NAME}.ccf
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cd build && \
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${PNRTOOL} -i ../${DESIGN_NAME}.v -o $@ --ccf ../${DESIGN_NAME}.ccf $(PNRFLAGS) \
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2>&1 | tee p_r-report.txt && \
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mv ${DESIGN_NAME}*.bit ../$@
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# Post-synthesis simulation target
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syn_sim: ${DESIGN_NAME}.v
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iverilog -g2012 -o tb_${DESIGN_NAME}_syn.vvp ${DESIGN_NAME}.v tb_${DESIGN_NAME}.v /usr/local/share/yosys/gatemate/cells_sim.v
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vvp -N tb_${DESIGN_NAME}_syn.vvp -fst
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# Post-implementation simulation target
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imp_sim: ${DESIGN_NAME}.bit
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iverilog -g2012 -o tb_${DESIGN_NAME}_imp.vvp build/${DESIGN_NAME}_00.v tb_${DESIGN_NAME}.v /opt/cc-toolchain-linux/bin/p_r/cpelib.v
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vvp -N tb_${DESIGN_NAME}_imp.vvp -fst
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# FPGA FW load per JTAG
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prog: ${DESIGN_NAME}.bit
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openFPGALoader -b gatemate_evb_jtag $<
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clean :
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echo "# Cleaning files"
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rm -rf build ${DESIGN_NAME}.v ${DESIGN_NAME}_sim.v ${DESIGN_NAME}.vhd ${DESIGN_NAME}.bit *.vvp *.fst
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