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83 lines
2.0 KiB
83 lines
2.0 KiB
library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.env.all;
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entity tb_uart_reg is
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end entity tb_uart_reg;
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architecture sim of tb_uart_reg is
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signal s_clk : std_logic := '1';
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signal s_rst_n : std_logic := '0';
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signal s_led_n : std_logic_vector(3 downto 0);
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signal s_uart_rx : std_logic := '1';
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signal s_uart_tx : std_logic;
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constant c_baudrate : natural := 9600;
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constant c_period_ns : time := 1000000000 / c_baudrate * ns;
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begin
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dut : entity work.uart_reg
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port map (
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clk_i => s_clk,
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rst_n_i => s_rst_n,
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uart_rx_i => s_uart_rx,
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uart_tx_o => s_uart_tx,
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led_n_o => s_led_n
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);
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s_rst_n <= '1' after 120 ns;
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s_clk <= not s_clk after 50 ns;
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SendP : process is
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variable v_data : std_logic_vector(7 downto 0);
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begin
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wait until s_rst_n;
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wait until rising_edge(s_clk);
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wait for 200 us;
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for tx in 0 to 255 loop
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v_data := std_logic_vector(to_unsigned(tx, 8));
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report "UART send: 0x" & to_hstring(v_data);
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s_uart_rx <= '0';
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wait for c_period_ns;
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for i in 0 to 7 loop
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s_uart_rx <= v_data(i);
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wait for c_period_ns;
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end loop;
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s_uart_rx <= '1';
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wait for c_period_ns;
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end loop;
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wait;
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end process;
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ReceiveP : process is
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variable v_data : std_logic_vector(7 downto 0);
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begin
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wait until s_rst_n;
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wait until rising_edge(s_clk);
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for rx in 0 to 255 loop
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wait until not s_uart_tx;
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wait for c_period_ns; -- Skip start bit
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wait for c_period_ns/2;
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for i in 0 to 7 loop
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v_data(i) := s_uart_tx;
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wait for c_period_ns;
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end loop;
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report "UART recv: 0x" & to_hstring(v_data);
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assert v_data = std_logic_vector(to_unsigned(rx, 8))
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report "UART receive error, got 0x" & to_hstring(v_data) & ", expected 0x" & to_hstring(v_data)
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severity failure;
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end loop;
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wait for 200 us;
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report "Simulation finished :-)";
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stop(0);
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end process;
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end architecture;
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