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tmeissner
/
gatemate_experiments
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Activity
33
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2
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209 KiB
VHDL
71.6%
Makefile
13.9%
Verilog
8.7%
C
5.4%
Tcl
0.4%
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70f13efdb2
gatemate_experiments
/
uart_trng
/
sim
History
T. Meissner
0df7a047be
Add uart_trng design
2 years ago
..
Makefile
Add uart_trng design
2 years ago
tb_uart_trng.vhd
Add uart_trng design
2 years ago