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124 lines
4.5 KiB
124 lines
4.5 KiB
DESIGN_NAME := neorv32_aes
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NEORV32_CORE_DIR := ../../neorv32/rtl/core
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NEORV32_PKG := $(NEORV32_CORE_DIR)/neorv32_package.vhd
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NEORV32_APP_SRC := $(NEORV32_CORE_DIR)/neorv32_application_image.vhd
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NEORV32_TEMPLATES := ../../neorv32/rtl/processor_templates
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NEORV32_MEM_ENTITIES := \
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$(NEORV32_CORE_DIR)/neorv32_dmem.entity.vhd \
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$(NEORV32_CORE_DIR)/neorv32_imem.entity.vhd
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NEORV32_MEM_SRC := \
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$(NEORV32_CORE_DIR)/mem/neorv32_imem.default.vhd \
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$(NEORV32_CORE_DIR)/mem/neorv32_dmem.default.vhd
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NEORV32_CORE_SRC := \
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$(NEORV32_CORE_DIR)/neorv32_bootloader_image.vhd \
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$(NEORV32_CORE_DIR)/neorv32_boot_rom.vhd \
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$(NEORV32_CORE_DIR)/neorv32_bus_keeper.vhd \
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$(NEORV32_CORE_DIR)/neorv32_busswitch.vhd \
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$(NEORV32_CORE_DIR)/neorv32_cpu.vhd \
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$(NEORV32_CORE_DIR)/neorv32_cpu_alu.vhd \
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$(NEORV32_CORE_DIR)/neorv32_cpu_bus.vhd \
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$(NEORV32_CORE_DIR)/neorv32_cpu_control.vhd \
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$(NEORV32_CORE_DIR)/neorv32_cpu_cp_bitmanip.vhd \
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$(NEORV32_CORE_DIR)/neorv32_cpu_cp_cfu.vhd \
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$(NEORV32_CORE_DIR)/neorv32_cpu_cp_fpu.vhd \
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$(NEORV32_CORE_DIR)/neorv32_cpu_cp_muldiv.vhd \
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$(NEORV32_CORE_DIR)/neorv32_cpu_cp_shifter.vhd \
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$(NEORV32_CORE_DIR)/neorv32_cpu_decompressor.vhd \
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$(NEORV32_CORE_DIR)/neorv32_cpu_regfile.vhd \
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$(NEORV32_CORE_DIR)/neorv32_debug_dm.vhd \
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$(NEORV32_CORE_DIR)/neorv32_debug_dtm.vhd \
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$(NEORV32_CORE_DIR)/neorv32_fifo.vhd \
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$(NEORV32_CORE_DIR)/neorv32_gpio.vhd \
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$(NEORV32_CORE_DIR)/neorv32_gptmr.vhd \
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$(NEORV32_CORE_DIR)/neorv32_icache.vhd \
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$(NEORV32_CORE_DIR)/neorv32_mtime.vhd \
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$(NEORV32_CORE_DIR)/neorv32_neoled.vhd \
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$(NEORV32_CORE_DIR)/neorv32_onewire.vhd \
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$(NEORV32_CORE_DIR)/neorv32_pwm.vhd \
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$(NEORV32_CORE_DIR)/neorv32_slink.vhd \
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$(NEORV32_CORE_DIR)/neorv32_spi.vhd \
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$(NEORV32_CORE_DIR)/neorv32_sysinfo.vhd \
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$(NEORV32_CORE_DIR)/neorv32_trng.vhd \
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$(NEORV32_CORE_DIR)/neorv32_twi.vhd \
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$(NEORV32_CORE_DIR)/neorv32_uart.vhd \
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$(NEORV32_CORE_DIR)/neorv32_wdt.vhd \
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$(NEORV32_CORE_DIR)/neorv32_wishbone.vhd \
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$(NEORV32_CORE_DIR)/neorv32_xip.vhd \
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$(NEORV32_CORE_DIR)/neorv32_xirq.vhd \
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$(NEORV32_CORE_DIR)/neorv32_cfs.vhd \
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$(NEORV32_CORE_DIR)/neorv32_cfs_aes.vhd \
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$(NEORV32_CORE_DIR)/neorv32_top.vhd
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NEORV32_SRC := ${NEORV32_PKG} ${NEORV32_APP_SRC} ${NEORV32_MEM_ENTITIES} \
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${NEORV32_MEM_SRC} ${NEORV32_CORE_SRC}
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AES_DIR := ../../cryptocores/aes/rtl/vhdl
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CRYPTO_SRC := \
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$(AES_DIR)/aes_pkg.vhd \
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$(AES_DIR)/aes_enc.vhd \
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$(AES_DIR)/aes_dec.vhd \
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$(AES_DIR)/aes.vhd \
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$(AES_DIR)/../../../ctraes/rtl/vhdl/ctraes.vhd
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WORK_FILES := ../rtl/${DESIGN_NAME}.vhd
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GM_FILES := ../../lib/rtl_components.vhd
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GHDL_FLAGS := --std=08 --workdir=build -Pbuild
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YOSYSPIPE := -nomx8
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# -retime
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PNRFLAGS := -om 3 -cCP on
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PNRTOOL := $(shell which p_r)
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.PHONY: all syn imp prog syn_sim imp_sim
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all: imp
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syn: ${DESIGN_NAME}.v
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imp: ${DESIGN_NAME}.bit
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build/work-obj08.cf: ${WORK_FILES} build/gatemate-obj08.cf build/neorv32-obj08.cf
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ghdl -a ${GHDL_FLAGS} --work=work ${WORK_FILES}
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build/neorv32-obj08.cf: build/gatemate-obj08.cf build/cryptocores-obj08.cf ${NEORV32_SRC}
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ghdl -a $(GHDL_FLAGS) --work=neorv32 ${NEORV32_SRC}
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build/cryptocores-obj08.cf: ${CRYPTO_SRC}
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ghdl -a $(GHDL_FLAGS) --work=cryptocores ${CRYPTO_SRC}
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build/gatemate-obj08.cf: ${GM_FILES}
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mkdir -p build
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ghdl -a ${GHDL_FLAGS} --work=gatemate ${GM_FILES}
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# Synthesis target for implementation
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${DESIGN_NAME}.v: build/work-obj08.cf
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yosys -m ghdl -p 'ghdl ${GHDL_FLAGS} --warn-no-binding --no-formal ${DESIGN_NAME}; synth_gatemate -top $(DESIGN_NAME) ${YOSYSPIPE} -vlog $@' \
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2>&1 | tee build/yosys-report.txt
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# Implementation target for FPGA
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${DESIGN_NAME}.bit: ${DESIGN_NAME}.v ${DESIGN_NAME}.ccf
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cd build && \
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${PNRTOOL} -i ../${DESIGN_NAME}.v -o $@ --ccf ../${DESIGN_NAME}.ccf $(PNRFLAGS) \
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2>&1 | tee p_r-report.txt && \
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mv ${DESIGN_NAME}*.bit ../$@
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# Post-synthesis simulation target
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syn_sim: ${DESIGN_NAME}.v
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iverilog -g2012 -o tb_${DESIGN_NAME}_syn.vvp ${DESIGN_NAME}.v tb_${DESIGN_NAME}.v /usr/local/share/yosys/gatemate/cells_sim.v
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vvp -N tb_${DESIGN_NAME}_syn.vvp -fst
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# Post-implementation simulation target
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imp_sim: ${DESIGN_NAME}.bit
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iverilog -g2012 -o tb_${DESIGN_NAME}_imp.vvp build/${DESIGN_NAME}_00.v tb_${DESIGN_NAME}.v /opt/cc-toolchain-linux/bin/p_r/cpelib.v
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vvp -N tb_${DESIGN_NAME}_imp.vvp -fst
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# FPGA FW load per JTAG
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prog: ${DESIGN_NAME}.bit
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openFPGALoader -b gatemate_evb_jtag $<
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clean :
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echo "# Cleaning files"
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rm -rf build ${DESIGN_NAME}.v ${DESIGN_NAME}_sim.v ${DESIGN_NAME}.vhd ${DESIGN_NAME}.bit *.vvp *.fst
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