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80 lines
1.8 KiB
80 lines
1.8 KiB
library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.env.all;
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entity tb_uart_trng is
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end entity tb_uart_trng;
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architecture sim of tb_uart_trng is
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signal s_clk : std_logic := '1';
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signal s_rst_n : std_logic := '0';
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signal s_uart_tx : std_logic;
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constant c_baudrate : natural := 9600;
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constant c_period_ns : time := 1000000000 / c_baudrate * ns;
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procedure uart_send ( data : in std_logic_vector(7 downto 0);
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signal tx : out std_logic) is
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begin
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report "UART send: 0x" & to_hstring(data);
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tx <= '0';
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wait for c_period_ns;
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for i in 0 to 7 loop
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tx <= data(i);
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wait for c_period_ns;
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end loop;
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tx <= '1';
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wait for c_period_ns;
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end procedure;
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procedure uart_recv ( data : out std_logic_vector(7 downto 0);
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signal rx : in std_logic) is
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begin
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wait until not rx;
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wait for c_period_ns; -- Skip start bit
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wait for c_period_ns/2;
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for i in 0 to 7 loop
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data(i) := rx;
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wait for c_period_ns;
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end loop;
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report "UART recv: 0x" & to_hstring(data);
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end procedure;
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begin
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dut : entity work.uart_trng
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generic map (
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SIM => 1
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)
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port map (
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clk_i => s_clk,
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rst_n_i => s_rst_n,
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uart_tx_o => s_uart_tx
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);
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s_rst_n <= '1' after 120 ns;
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s_clk <= not s_clk after 50 ns;
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ReceiveP : process is
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type t_exp is array (0 to 7) of std_logic_vector(7 downto 0);
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variable v_exp : t_exp;
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variable v_data : std_logic_vector(7 downto 0);
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begin
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wait until s_rst_n;
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wait until rising_edge(s_clk);
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-- First read all registers
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for i in 0 to 7 loop
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uart_recv(v_data, s_uart_tx);
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end loop;
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wait for 200 us;
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report "Simulation finished :-)";
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stop(0);
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end process;
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end architecture;
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