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116 lines
2.7 KiB
116 lines
2.7 KiB
-- This design should display incrementing binary numbers
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-- at LED1-LED8 of the GateMate FPGA Starter Kit.
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library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library gatemate;
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use gatemate.components.all;
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entity blink is
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generic (
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SIM : natural := 0
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);
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port (
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clk_i : in std_logic; -- 10 MHz clock
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rst_n_i : in std_logic; -- SW3 button
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led_n_o : out std_logic_vector(7 downto 0) -- LED1..LED8
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);
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end entity blink;
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architecture rtl of blink is
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subtype t_clk_cnt is unsigned(19 downto 0);
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signal s_clk_cnt : t_clk_cnt;
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signal s_clk_cnt_end : t_clk_cnt;
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signal s_pll_clk : std_logic;
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signal s_pll_lock : std_logic;
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signal s_clk_en : boolean;
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signal s_rst_n : std_logic;
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signal s_cfg_end : std_logic;
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signal s_sys_rst_n : std_logic;
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begin
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pll : CC_PLL
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generic map (
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REF_CLK => "10",
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OUT_CLK => "2",
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PERF_MD => "ECONOMY"
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)
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port map (
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CLK_REF => clk_i,
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CLK_FEEDBACK => '0',
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USR_CLK_REF => '0',
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USR_LOCKED_STDY_RST => '0',
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USR_PLL_LOCKED_STDY => open,
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USR_PLL_LOCKED => s_pll_lock,
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CLK270 => open,
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CLK180 => open,
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CLK0 => s_pll_clk,
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CLK90 => open,
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CLK_REF_OUT => open
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);
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cfg_end_inst : CC_CFG_END
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port map (
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CFG_END => s_cfg_end
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);
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-- This works
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s_rst_n <= rst_n_i and s_pll_lock and s_cfg_end;
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-- This doesn't work.
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-- The reset module seems to be removed during Yosys flatten pass, even
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-- when the output is connected with an output port, WHY does this happen?
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-- 2.5. Executing FLATTEN pass (flatten design).
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-- Deleting now unused module reset_sync_c4ea21bb365bbeeaf5f2c654883e56d11e43c44e.
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-- <suppressed ~1 debug messages>
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reset : entity work.reset_sync
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generic map (
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POLARITY => '0'
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)
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port map (
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clk_i => s_pll_clk,
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rst_i => rst_n_i and s_pll_lock and s_cfg_end,
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rst_o => s_sys_rst_n
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);
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s_clk_cnt_end <= 20x"FFFFF" when SIM = 0 else -- synthesis
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20x"000FF"; -- simulation
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process (s_pll_clk, s_rst_n) is
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begin
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if (not s_rst_n) then
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s_clk_cnt <= (others => '0');
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elsif (rising_edge(s_pll_clk)) then
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if (s_clk_cnt = s_clk_cnt_end) then
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s_clk_cnt <= (others => '0');
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else
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s_clk_cnt <= s_clk_cnt + 1;
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end if;
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end if;
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end process;
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s_clk_en <= s_clk_cnt = s_clk_cnt_end;
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process (s_pll_clk, s_rst_n) is
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begin
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if (not s_rst_n) then
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led_n_o <= x"FE";
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elsif (rising_edge(s_pll_clk)) then
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if (s_clk_en) then
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led_n_o <= led_n_o(6 downto 0) & led_n_o(7);
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end if;
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end if;
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end process;
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end architecture;
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