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209 lines
7.1 KiB
209 lines
7.1 KiB
-- UART register
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-- Register file with 8 registers storing values of one byte each.
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--
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-- The first received byte on the axis in port contains command & address:
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--
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-- 7 reserved
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-- 6:4 register address
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-- 3:0 command
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-- 0x0 read
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-- 0x1 write
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--
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-- In case of a write command, the payload has to follow
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-- with the next byte.
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--
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-- In case of a read command, the value of the addressed
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-- register is returned on the axis out port.
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--
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-- Register at address 0 is special. It contains the version
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-- and is read-only. Writes to that register are ignored.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.uart_aes_types.all;
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entity uart_ctrl is
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port (
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-- globals
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rst_n_i : in std_logic;
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clk_i : in std_logic;
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-- axis in
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tdata_i : in std_logic_vector(7 downto 0);
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tvalid_i : in std_logic;
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tready_o : out std_logic;
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-- axis out
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tdata_o : out std_logic_vector(7 downto 0);
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tvalid_o : out std_logic;
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tready_i : in std_logic;
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-- aes out
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ctrl_aes_o : out t_axis_ctrl_aes_m2s;
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ctrl_aes_i : in t_axis_s2m;
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-- aes in
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aes_ctrl_i : in t_axis_aes_ctrl_m2s;
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aes_ctrl_o : out t_axis_s2m
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);
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end entity uart_ctrl;
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architecture rtl of uart_ctrl is
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type t_state is (IDLE, GET_CMD, RECV_DATA, SEND_DATA);
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signal s_state : t_state;
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signal s_reg_file : t_reg_file;
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signal s_reg_addr : natural range 0 to 7;
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signal s_reg_data : std_logic_vector(7 downto 0);
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subtype t_cmd is std_ulogic_vector(3 downto 0);
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constant c_read : t_cmd := x"0";
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constant c_write : t_cmd := x"1";
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alias a_tdata_cmd is tdata_i(3 downto 0);
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alias a_tdata_addr is tdata_i(6 downto 4);
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constant c_ctrl_addr : natural := 0;
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constant c_key_addr : natural := 1;
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constant c_nonce_addr : natural := 2;
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constant c_din_addr : natural := 3;
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constant c_out_addr : natural := 4;
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constant AES_RESET : natural := 0; -- Reset key & din registers
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constant CTR_START : natural := 1; -- 1st round of counter mode
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constant AES_START : natural := 2; -- start AES engine (cleared with AES_END)
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constant AES_END : natural := 3; -- AES engine finished
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type reg_acc_cnt_t is array (natural range <>) of unsigned(3 downto 0);
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signal read_acc_cnt : reg_acc_cnt_t(0 to 3);
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signal write_acc_cnt : reg_acc_cnt_t(0 to 2);
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begin
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-- Register memory
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process (clk_i, rst_n_i) is
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begin
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if (not rst_n_i) then
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s_reg_data <= (others => '0');
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s_reg_file <= c_reg_file_init;
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read_acc_cnt <= (others => x"0");
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write_acc_cnt <= (others => x"0");
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elsif (rising_edge(clk_i)) then
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-- Register write
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if (s_state = RECV_DATA and tvalid_i = '1') then
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case s_reg_addr is
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when 0 => s_reg_file.ctrl <= tdata_i;
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-- Clear all regs when AES_RESET bit set
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if (tdata_i(AES_RESET)) then
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s_reg_file.ctrl <= (others => '0');
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s_reg_file.key <= (others => '0');
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s_reg_file.nonce <= (others => '0');
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s_reg_file.din <= (others => '0');
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write_acc_cnt <= (others => x"0");
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read_acc_cnt <= (others => x"0");
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end if;
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when 1 => write_acc_cnt(0) <= write_acc_cnt(0) + 1;
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s_reg_file.key(to_integer(write_acc_cnt(0))*8 to to_integer(write_acc_cnt(0))*8+7) <= tdata_i;
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when 2 => if (write_acc_cnt(1) = 11) then
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write_acc_cnt(1) <= x"0";
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else
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write_acc_cnt(1) <= write_acc_cnt(1) + 1;
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end if;
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s_reg_file.nonce(to_integer(write_acc_cnt(1))*8 to to_integer(write_acc_cnt(1))*8+7) <= tdata_i;
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when 3 => write_acc_cnt(2) <= write_acc_cnt(2) + 1;
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s_reg_file.din(to_integer(write_acc_cnt(2))*8 to to_integer(write_acc_cnt(2))*8+7) <= tdata_i;
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when others => null;
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end case;
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end if;
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-- Register read
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aes_ctrl_o.tready <= '0';
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if (s_state = GET_CMD and a_tdata_cmd = c_read) then
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case s_reg_addr is
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when 0 => s_reg_data <= s_reg_file.ctrl;
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when 1 => read_acc_cnt(0) <= read_acc_cnt(0) + 1;
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s_reg_data <= s_reg_file.key(to_integer(read_acc_cnt(0))*8 to to_integer(read_acc_cnt(0))*8+7);
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when 2 => if (read_acc_cnt(1) = 11) then
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read_acc_cnt(1) <= x"0";
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else
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read_acc_cnt(1) <= read_acc_cnt(1) + 1;
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end if;
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s_reg_data <= s_reg_file.nonce(to_integer(read_acc_cnt(1))*8 to to_integer(read_acc_cnt(1))*8+7);
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when 3 => read_acc_cnt(2) <= read_acc_cnt(2) + 1;
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s_reg_data <= s_reg_file.din(to_integer(read_acc_cnt(2))*8 to to_integer(read_acc_cnt(2))*8+7);
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when 4 => read_acc_cnt(3) <= read_acc_cnt(3) + 1;
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s_reg_data <= aes_ctrl_i.tdata(to_integer(read_acc_cnt(3))*8 to to_integer(read_acc_cnt(3))*8+7);
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if (read_acc_cnt(3) = 15) then
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aes_ctrl_o.tready <= aes_ctrl_i.tvalid;
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end if;
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when others => s_reg_data <= (others => '0');
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end case;
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end if;
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-- Set AES_END when AES out data is valid
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-- Reset when AES out data was accepted (all 16 bytes of AES output data were read)
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if (aes_ctrl_o.tready) then
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s_reg_file.ctrl(AES_END) <= '0';
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elsif (aes_ctrl_i.tvalid) then
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s_reg_file.ctrl(AES_END) <= '1';
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end if;
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-- Reset AES_START & CTR_START when AES engine accepts in data
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if (ctrl_aes_i.tready and s_reg_file.ctrl(AES_START)) then
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s_reg_file.ctrl(AES_START) <= '0';
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s_reg_file.ctrl(CTR_START) <= '0';
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end if;
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end if;
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end process;
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-- Control state machine
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process (clk_i, rst_n_i) is
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begin
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if (not rst_n_i) then
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s_state <= IDLE;
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s_reg_addr <= 0;
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elsif (rising_edge(clk_i)) then
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case s_state is
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when IDLE =>
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if (tvalid_i) then
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s_state <= GET_CMD;
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s_reg_addr <= to_integer(unsigned(a_tdata_addr));
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end if;
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when GET_CMD =>
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if (a_tdata_cmd = c_read) then
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s_state <= SEND_DATA;
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elsif (a_tdata_cmd = c_write) then
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s_state <= RECV_DATA;
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else
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s_state <= IDLE;
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end if;
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when RECV_DATA =>
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if (tvalid_i) then
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s_state <= IDLE;
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end if;
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when SEND_DATA =>
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if (tready_i) then
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s_state <= IDLE;
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end if;
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when others =>
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null;
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end case;
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end if;
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end process;
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tready_o <= '1' when s_state = GET_CMD or s_state = RECV_DATA else '0';
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tdata_o <= s_reg_data;
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tvalid_o <= '1' when s_state = SEND_DATA else '0';
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ctrl_aes_o.tuser.start <= s_reg_file.ctrl(CTR_START);
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ctrl_aes_o.tuser.key <= s_reg_file.key;
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ctrl_aes_o.tuser.nonce <= s_reg_file.nonce;
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ctrl_aes_o.tdata <= s_reg_file.din;
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ctrl_aes_o.tvalid <= s_reg_file.ctrl(AES_START);
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end architecture;
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