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102 lines
2.2 KiB
102 lines
2.2 KiB
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
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`define USE_RAM
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// simplified CC_PLL model
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module CC_PLL #(
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parameter REF_CLK = "", // e.g. "10.0"
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parameter OUT_CLK = "", // e.g. "50.0"
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parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED
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parameter LOW_JITTER = 1,
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parameter CI_FILTER_CONST = 2,
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parameter CP_FILTER_CONST = 4
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)(
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input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
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input USR_LOCKED_STDY_RST, USR_SET_SEL,
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output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
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output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
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);
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reg r_pll_clk;
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reg r_user_pll_locked;
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// OUT_FREQ = 10 MHz
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localparam clk_half_period = 50;
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initial begin
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r_pll_clk = 1'b0;
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r_user_pll_locked = 1'b1;
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end
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always #clk_half_period r_pll_clk = ~r_pll_clk;
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assign CLK0 = r_pll_clk;
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assign USR_PLL_LOCKED = r_user_pll_locked;
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endmodule
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// simplified CC_CFG_END model
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module CC_CFG_END (
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output CFG_END
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);
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assign CFG_END = 1'b1;
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endmodule
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module tb_neorv32_aes;
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// DUT in/out
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reg clk = 1'b0;
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reg rst_n = 1'b1;
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wire [7:0] led;
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wire [63:0] debug;
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reg uart_rx;
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wire uart_tx;
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// Testbench variables
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// Testbench 1/2 clock period
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localparam clk_half_period = 50;
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// UART period calculation (9600 baud)
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localparam uart_bit_period = 1000000000 / 9600;
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localparam uart_bit_half_period = uart_bit_period/2;
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neorv32_aes UUT (.clk_i(clk), .rst_n_i(rst_n), .led_n_o(led), .debug_o(debug));
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// neorv32_aes UUT (.clk_i(clk), .rst_n_i(rst_n), .led_n_o(led), .uart_tx_o(uart_tx), .uart_rx_i(uart_rx));
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// set dumpfile
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initial begin
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$dumpfile ("tb_neorv32_aes.fst");
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$dumpvars (0, tb_neorv32_aes);
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end
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// Setup simulation
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initial begin
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uart_rx = 1'b1;
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#1 rst_n = 1'b0;
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#120 rst_n = 1'b1;
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end
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// Generate 10 mhz clock
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always #clk_half_period clk = !clk;
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// Stimuli generator
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initial
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forever @(posedge rst_n) begin
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// Simulate for 100 us
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#500_000
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// @(negedge led[0]);
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// #100
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$display ("NEORV32 test finished");
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$finish;
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end
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// Monitor
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initial begin
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$monitor("monitor time=%t ns, rst_n=%b, led=%b, imem.addr=%d, dmem.addr=%h", $time, rst_n, led, debug[31:2], debug[63:32]);
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end
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endmodule
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