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73 lines
2.1 KiB
73 lines
2.1 KiB
library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.env.all;
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use work.uart_aes_ref.all;
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entity tb_uart_aes is
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end entity tb_uart_aes;
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architecture sim of tb_uart_aes is
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signal s_clk : std_logic := '1';
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signal s_rst_n : std_logic := '0';
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signal s_uart_rx : std_logic := '1';
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signal s_uart_tx : std_logic;
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constant c_baudrate : natural := 9600;
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constant c_period_ns : time := 1_000_000_000 / c_baudrate * ns;
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package uart_aes_sim_inst is new work.uart_aes_sim
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generic map (period_ns => c_period_ns);
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use uart_aes_sim_inst.all;
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begin
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dut : entity work.uart_aes
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port map (
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clk_i => s_clk,
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rst_n_i => s_rst_n,
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uart_rx_i => s_uart_rx,
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uart_tx_o => s_uart_tx
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);
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s_rst_n <= '1' after 120 ns;
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s_clk <= not s_clk after 50 ns;
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TestP : process is
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variable v_data : std_logic_vector(7 downto 0);
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variable v_uart_data : std_logic_vector(0 to 127);
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variable v_key : std_logic_vector(0 to 127);
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variable v_nonce : std_logic_vector(0 to 95);
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variable v_in_data : std_logic_vector(0 to 127);
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variable v_ref_data : std_logic_vector(0 to 127);
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begin
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wait until s_rst_n;
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wait until rising_edge(s_clk);
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wait for 200 us;
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v_key := x"0123456789ABCDEF0123456789ABCDEF";
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v_nonce := x"0123456789ABCDEF01234567";
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aes_setup(v_key, v_nonce, s_uart_rx);
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for i in 0 to 7 loop
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report "Test round " & to_string(i);
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v_in_data := x"0123456789ABCDEF0123456789ABCDEF";
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aes_write(v_in_data, s_uart_rx);
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aes_crypt(s_uart_rx, s_uart_tx);
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aes_read(v_uart_data, s_uart_rx, s_uart_tx);
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-- Calc reference data
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cryptData(swap(v_in_data), swap(v_key), swap(v_nonce & 32x"0"), i=0, i=7, v_ref_data, v_in_data'length/8);
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assert v_uart_data = swap(v_ref_data)
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report "Encryption error: Expected 0x" & to_hstring(swap(v_ref_data)) & ", got 0x" & to_hstring(v_uart_data)
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severity failure;
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end loop;
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wait for 100 us;
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report "Simulation finished without errors";
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stop(0);
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end process;
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end architecture;
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