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26 lines
641 B
26 lines
641 B
DESIGN_NAME := blink
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RTL_SRC := ../rtl/${DESIGN_NAME}.vhd
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SIM_SRC := tb_${DESIGN_NAME}.vhd
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VHD_STD := 08
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.PHONY: all compile sim clean
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all: sim
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compile: tb_${DESIGN_NAME}
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tb_${DESIGN_NAME}: ${RTL_SRC} ${SIM_SRC} | work
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@echo "Analyze testbench & design ..."
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ghdl -a --std=${VHD_STD} -fpsl --workdir=work ${RTL_SRC} ${SIM_SRC}
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@echo "Elaborate testbench & design ..."
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ghdl -e --std=${VHD_STD} -fpsl --workdir=work $@
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sim: tb_${DESIGN_NAME}
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@echo "Run testbench ..."
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ghdl -r tb_${DESIGN_NAME} --assert-level=error
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work:
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mkdir $@
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clean:
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@echo "Cleaning simulation files ..."
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rm -rf tb_${DESIGN_NAME} *.o *.json work/
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