Library of reusable VHDL components
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. --+ including vhdl 2008 libraries
  5. --+ These lines can be commented out when using
  6. --+ a simulator with built-in VHDL 2008 support
  7. --library ieee_proposed;
  8. -- use ieee_proposed.standard_additions.all;
  9. -- use ieee_proposed.std_logic_1164_additions.all;
  10. -- use ieee_proposed.numeric_std_additions.all;
  11. library osvvm;
  12. use osvvm.RandomPkg.all;
  13. library libvhdl;
  14. use libvhdl.AssertP.all;
  15. use libvhdl.SimP.all;
  16. use libvhdl.QueueP.all;
  17. entity WishBoneT is
  18. end entity WishBoneT;
  19. architecture sim of WishBoneT is
  20. component WishBoneMasterE is
  21. generic (
  22. G_ADR_WIDTH : positive := 8; --* address bus width
  23. G_DATA_WIDTH : positive := 8 --* data bus width
  24. );
  25. port (
  26. --+ wishbone system if
  27. WbRst_i : in std_logic;
  28. WbClk_i : in std_logic;
  29. --+ wishbone outputs
  30. WbCyc_o : out std_logic;
  31. WbStb_o : out std_logic;
  32. WbWe_o : out std_logic;
  33. WbAdr_o : out std_logic_vector(G_ADR_WIDTH-1 downto 0);
  34. WbDat_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
  35. --+ wishbone inputs
  36. WbDat_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
  37. WbAck_i : in std_logic;
  38. WbErr_i : in std_logic;
  39. --+ local register if
  40. LocalWen_i : in std_logic;
  41. LocalRen_i : in std_logic;
  42. LocalAdress_i : in std_logic_vector(G_ADR_WIDTH-1 downto 0);
  43. LocalData_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
  44. LocalData_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
  45. LocalAck_o : out std_logic;
  46. LocalError_o : out std_logic
  47. );
  48. end component WishBoneMasterE;
  49. component WishBoneSlaveE is
  50. generic (
  51. G_ADR_WIDTH : positive := 8; --* address bus width
  52. G_DATA_WIDTH : positive := 8 --* data bus width
  53. );
  54. port (
  55. --+ wishbone system if
  56. WbRst_i : in std_logic;
  57. WbClk_i : in std_logic;
  58. --+ wishbone inputs
  59. WbCyc_i : in std_logic;
  60. WbStb_i : in std_logic;
  61. WbWe_i : in std_logic;
  62. WbAdr_i : in std_logic_vector(G_ADR_WIDTH-1 downto 0);
  63. WbDat_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
  64. --* wishbone outputs
  65. WbDat_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
  66. WbAck_o : out std_logic;
  67. WbErr_o : out std_logic;
  68. --+ local register if
  69. LocalWen_o : out std_logic;
  70. LocalRen_o : out std_logic;
  71. LocalAdress_o : out std_logic_vector(G_ADR_WIDTH-1 downto 0);
  72. LocalData_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
  73. LocalData_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0)
  74. );
  75. end component WishBoneSlaveE;
  76. --* testbench global clock period
  77. constant C_PERIOD : time := 5 ns;
  78. --* Wishbone data width
  79. constant C_DATA_WIDTH : natural := 8;
  80. --* Wishbone address width
  81. constant C_ADDRESS_WIDTH : natural := 8;
  82. --* testbench global clock
  83. signal s_wb_clk : std_logic := '1';
  84. --* testbench global reset
  85. signal s_wb_reset : std_logic := '1';
  86. --+ test done array with entry for each test
  87. signal s_test_done : boolean;
  88. signal s_wb_cyc : std_logic;
  89. signal s_wb_stb : std_logic;
  90. signal s_wb_we : std_logic;
  91. signal s_wb_adr : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0);
  92. signal s_wb_master_data : std_logic_vector(C_DATA_WIDTH-1 downto 0);
  93. signal s_wb_slave_data : std_logic_vector(C_DATA_WIDTH-1 downto 0);
  94. signal s_wb_ack : std_logic;
  95. signal s_wb_err : std_logic;
  96. signal s_master_local_wen : std_logic;
  97. signal s_master_local_ren : std_logic;
  98. signal s_master_local_adress : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0);
  99. signal s_master_local_din : std_logic_vector(C_DATA_WIDTH-1 downto 0);
  100. signal s_master_local_dout : std_logic_vector(C_DATA_WIDTH-1 downto 0);
  101. signal s_master_local_ack : std_logic;
  102. signal s_master_local_error : std_logic;
  103. signal s_slave_local_wen : std_logic;
  104. signal s_slave_local_ren : std_logic;
  105. signal s_slave_local_adress : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0);
  106. signal s_slave_local_dout : std_logic_vector(C_DATA_WIDTH-1 downto 0);
  107. signal s_slave_local_din : std_logic_vector(C_DATA_WIDTH-1 downto 0);
  108. type t_register is array (0 to integer'(2**C_ADDRESS_WIDTH-1)) of std_logic_vector(C_DATA_WIDTH-1 downto 0);
  109. shared variable sv_wishbone_queue : t_list_queue;
  110. begin
  111. --* testbench global clock
  112. s_wb_clk <= not(s_wb_clk) after C_PERIOD/2 when not(s_test_done) else '0';
  113. --* testbench global reset
  114. s_wb_reset <= '0' after C_PERIOD * 5;
  115. QueueInitP : process is
  116. begin
  117. sv_wishbone_queue.init(2**C_ADDRESS_WIDTH);
  118. wait;
  119. end process QueueInitP;
  120. WbMasterLocalP : process is
  121. variable v_random : RandomPType;
  122. variable v_wbmaster_data : std_logic_vector(C_DATA_WIDTH-1 downto 0);
  123. begin
  124. v_random.InitSeed(v_random'instance_name);
  125. v_wbmaster_data := (others => '0');
  126. s_master_local_din <= (others => '0');
  127. s_master_local_adress <= (others => '0');
  128. s_master_local_wen <= '0';
  129. s_master_local_ren <= '0';
  130. wait until s_wb_reset = '0';
  131. -- write the wishbone slave registers
  132. for i in 0 to integer'(2**C_ADDRESS_WIDTH-1) loop
  133. v_wbmaster_data := v_random.RandSlv(C_DATA_WIDTH);
  134. s_master_local_din <= v_wbmaster_data;
  135. s_master_local_adress <= std_logic_vector(to_unsigned(i, C_ADDRESS_WIDTH));
  136. s_master_local_wen <= '1';
  137. wait until rising_edge(s_wb_clk);
  138. s_master_local_din <= (others => '0');
  139. s_master_local_adress <= (others => '0');
  140. s_master_local_wen <= '0';
  141. wait until rising_edge(s_wb_clk) and s_master_local_ack = '1';
  142. sv_wishbone_queue.push(v_wbmaster_data);
  143. end loop;
  144. -- read back and check the wishbone slave registers
  145. for i in 0 to integer'(2**C_ADDRESS_WIDTH-1) loop
  146. s_master_local_adress <= std_logic_vector(to_unsigned(i, C_ADDRESS_WIDTH));
  147. s_master_local_ren <= '1';
  148. wait until rising_edge(s_wb_clk);
  149. s_master_local_adress <= (others => '0');
  150. s_master_local_ren <= '0';
  151. wait until rising_edge(s_wb_clk) and s_master_local_ack = '1';
  152. sv_wishbone_queue.pop(v_wbmaster_data);
  153. assert_equal(s_master_local_dout, v_wbmaster_data);
  154. end loop;
  155. report "INFO: Test successfully finished!";
  156. s_test_done <= true;
  157. wait;
  158. end process WbMasterLocalP;
  159. i_WishBoneMasterE : WishBoneMasterE
  160. generic map (
  161. G_ADR_WIDTH => C_ADDRESS_WIDTH,
  162. G_DATA_WIDTH => C_DATA_WIDTH
  163. )
  164. port map (
  165. --+ wishbone system if
  166. WbRst_i => s_wb_reset,
  167. WbClk_i => s_wb_clk,
  168. --+ wishbone outputs
  169. WbCyc_o => s_wb_cyc,
  170. WbStb_o => s_wb_stb,
  171. WbWe_o => s_wb_we,
  172. WbAdr_o => s_wb_adr,
  173. WbDat_o => s_wb_master_data,
  174. --+ wishbone inputs
  175. WbDat_i => s_wb_slave_data,
  176. WbAck_i => s_wb_ack,
  177. WbErr_i => s_wb_err,
  178. --+ local register if
  179. LocalWen_i => s_master_local_wen,
  180. LocalRen_i => s_master_local_ren,
  181. LocalAdress_i => s_master_local_adress,
  182. LocalData_i => s_master_local_din,
  183. LocalData_o => s_master_local_dout,
  184. LocalAck_o => s_master_local_ack,
  185. LocalError_o => s_master_local_error
  186. );
  187. WishBoneBusMonitorP : process is
  188. variable v_master_local_adress : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0);
  189. variable v_master_local_data : std_logic_vector(C_DATA_WIDTH-1 downto 0);
  190. begin
  191. wait until s_master_local_wen = '1';
  192. v_master_local_adress := s_master_local_adress;
  193. v_master_local_data := s_master_local_din;
  194. wait until s_wb_cyc = '1';
  195. WB_ADDR : assert s_wb_adr = v_master_local_adress
  196. report "ERROR: Wishbone address 0x" & to_hstring(s_wb_adr) & " differ from local address 0x" & to_hstring(v_master_local_adress)
  197. severity failure;
  198. if (s_wb_we = '1') then
  199. WB_DATA : assert s_wb_master_data = v_master_local_data
  200. report "ERROR: Wishbone data 0x" & to_hstring(s_wb_master_data) & " differ from local data 0x" & to_hstring(v_master_local_data)
  201. severity failure;
  202. end if;
  203. end process WishBoneBusMonitorP;
  204. i_WishBoneSlaveE : WishBoneSlaveE
  205. generic map (
  206. G_ADR_WIDTH => C_ADDRESS_WIDTH,
  207. G_DATA_WIDTH => C_DATA_WIDTH
  208. )
  209. port map (
  210. --+ wishbone system if
  211. WbRst_i => s_wb_reset,
  212. WbClk_i => s_wb_clk,
  213. --+ wishbone inputs
  214. WbCyc_i => s_wb_cyc,
  215. WbStb_i => s_wb_stb,
  216. WbWe_i => s_wb_we,
  217. WbAdr_i => s_wb_adr,
  218. WbDat_i => s_wb_master_data,
  219. --* wishbone outputs
  220. WbDat_o => s_wb_slave_data,
  221. WbAck_o => s_wb_ack,
  222. WbErr_o => s_wb_err,
  223. --+ local register if
  224. LocalWen_o => s_slave_local_wen,
  225. LocalRen_o => s_slave_local_ren,
  226. LocalAdress_o => s_slave_local_adress,
  227. LocalData_o => s_slave_local_dout,
  228. LocalData_i => s_slave_local_din
  229. );
  230. WbSlaveLocalP : process is
  231. variable v_register : t_register := (others => (others => '0'));
  232. begin
  233. wait until rising_edge(s_wb_clk);
  234. if (s_wb_reset = '1') then
  235. v_register := (others => (others => '0'));
  236. s_slave_local_din <= (others => '0');
  237. else
  238. if (s_slave_local_wen = '1') then
  239. v_register(to_integer(unsigned(s_slave_local_adress))) := s_slave_local_dout;
  240. elsif (s_slave_local_ren = '1') then
  241. s_slave_local_din <= v_register(to_integer(unsigned(s_slave_local_adress)));
  242. end if;
  243. end if;
  244. end process WbSlaveLocalP;
  245. end architecture sim;