Library of reusable VHDL components
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. library libvhdl;
  5. use libvhdl.StringP.all;
  6. use libvhdl.AssertP.all;
  7. entity StringT is
  8. end entity StringT;
  9. architecture sim of StringT is
  10. begin
  11. StringTestP : process is
  12. variable v_data : std_logic_vector(31 downto 0) := x"DEADBEEF";
  13. variable v_data_reverse : std_logic_vector(0 to 31) := x"DEADBEEF";
  14. begin
  15. assert_equal(to_string(v_data(0)), "1");
  16. assert_equal(to_string(v_data), "11011110101011011011111011101111");
  17. assert_equal(to_string(v_data_reverse), "11011110101011011011111011101111");
  18. report "INFO: StringP tests finished successfully";
  19. wait;
  20. end process StringTestP;
  21. end architecture sim;