Library of reusable VHDL components
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

88 lines
1.9 KiB

  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. package UtilsP is
  5. function and_reduce (data : in std_logic_vector) return std_logic;
  6. function and_reduce (data : in boolean_vector) return boolean;
  7. function or_reduce (data : in std_logic_vector) return std_logic;
  8. function or_reduce (data : in boolean_vector) return boolean;
  9. function even_parity (data : in std_logic_vector) return std_logic;
  10. function odd_parity (data : in std_logic_vector) return std_logic;
  11. end package UtilsP;
  12. package body UtilsP is
  13. function and_reduce (data : in std_logic_vector) return std_logic is
  14. begin
  15. for i in data'range loop
  16. if data(i) = '0' then
  17. return '0';
  18. end if;
  19. end loop;
  20. return '1';
  21. end function and_reduce;
  22. function and_reduce (data : in boolean_vector) return boolean is
  23. begin
  24. for i in data'range loop
  25. if (not(data(i))) then
  26. return false;
  27. end if;
  28. end loop;
  29. return true;
  30. end function and_reduce;
  31. function or_reduce (data : in std_logic_vector) return std_logic is
  32. begin
  33. for i in data'range loop
  34. if data(i) = '1' then
  35. return '1';
  36. end if;
  37. end loop;
  38. return '0';
  39. end function or_reduce;
  40. function or_reduce (data : in boolean_vector) return boolean is
  41. begin
  42. for i in data'range loop
  43. if data(i) then
  44. return true;
  45. end if;
  46. end loop;
  47. return false;
  48. end function or_reduce;
  49. function even_parity (data : in std_logic_vector) return std_logic is
  50. variable v_return : std_logic := '0';
  51. begin
  52. for i in data'range loop
  53. v_return := v_return xor data(i);
  54. end loop;
  55. return v_return;
  56. end function even_parity;
  57. function odd_parity (data : in std_logic_vector) return std_logic is
  58. variable v_return : std_logic := '1';
  59. begin
  60. for i in data'range loop
  61. v_return := v_return xor data(i);
  62. end loop;
  63. return v_return;
  64. end function odd_parity;
  65. end package body UtilsP;