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@ -57,7 +57,7 @@ begin |
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WbReadC : case s_wb_master_fsm is |
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when IDLE => |
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if (LocalWen_i = '1' or LocalRen_i = '1') then |
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if ((LocalWen_i xor LocalRen_i) = '1') then |
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s_wb_master_fsm <= ADDRESS; |
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end if; |
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@ -103,7 +103,7 @@ begin |
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s_wb_wen <= '0'; |
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else |
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if (s_wb_master_fsm = IDLE) then |
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if (LocalWen_i = '1' or LocalRen_i = '1') then |
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if ((LocalWen_i xor LocalRen_i) = '1') then |
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WbAdr_o <= LocalAdress_i; |
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s_wb_wen <= LocalWen_i; |
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end if; |
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@ -117,16 +117,40 @@ begin |
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-- psl default clock is rising_edge(WbClk_i); |
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-- PSL assert directives |
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-- psl RESET : assert always |
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-- WbRst_i -> |
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-- WbCyc_o = '0' and WbStb_o = '0' and WbWe_o = '0' and |
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-- to_integer(unsigned(WbAdr_o)) = 0 and to_integer(unsigned(WbDat_o)) = 0 and |
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-- LocalAck_o = '0' and LocalError_o = '0' and to_integer(unsigned(LocalData_o)) = 0 |
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-- report "WB master: Reset error"; |
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-- |
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-- psl WB_WRITE : assert always |
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-- ((not(WbCyc_o) and not(WbStb_o) and LocalWen_i) -> |
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-- ((not(WbCyc_o) and not(WbStb_o) and LocalWen_i and not (LocalRen_i)) -> |
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-- next (WbCyc_o = '1' and WbStb_o = '1' and WbWe_o = '1')) abort WbRst_i |
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-- report "PSL ERROR: Wishbone write error"; |
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-- report "WB master: Write error"; |
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-- |
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-- psl WB_READ : assert always |
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-- ((not(WbCyc_o) and not(WbStb_o) and LocalRen_i) |-> |
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-- ((not(WbCyc_o) and not(WbStb_o) and LocalRen_i and not(LocalWen_i)) |-> |
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-- next (WbCyc_o = '1' and WbStb_o = '1' and WbWe_o = '0')) abort WbRst_i |
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-- report "PSL ERROR: Wishbone read error"; |
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-- report "WB master: Read error"; |
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-- PSL cover directives |
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-- psl COVER_LOCAL_WRITE : cover {s_wb_master_fsm = IDLE and LocalWen_i = '1' and |
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-- LocalRen_i = '0' and WbRst_i = '0'} |
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-- report "WB master: Local write"; |
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-- |
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-- psl COVER_LOCAL_READ : cover {s_wb_master_fsm = IDLE and LocalRen_i = '1' and |
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-- LocalWen_i = '0' and WbRst_i = '0'} |
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-- report "WB master: Local read"; |
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-- |
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-- psl COVER_LOCAL_WRITE_READ : cover {s_wb_master_fsm = IDLE and LocalWen_i = '1' and |
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-- LocalRen_i = '1' and WbRst_i = '0'} |
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-- report "WB master: Local write & read"; |
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end architecture rtl; |