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@ -2,14 +2,6 @@ library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.numeric_std.all; |
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--+ including vhdl 2008 libraries |
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--+ These lines can be commented out when using |
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--+ a simulator with built-in VHDL 2008 support |
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--library ieee_proposed; |
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-- use ieee_proposed.standard_additions.all; |
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-- use ieee_proposed.std_logic_1164_additions.all; |
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-- use ieee_proposed.numeric_std_additions.all; |
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library osvvm; |
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use osvvm.RandomPkg.all; |
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use osvvm.CoveragePkg.all; |
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@ -18,9 +10,11 @@ library libvhdl; |
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use libvhdl.AssertP.all; |
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use libvhdl.SimP.all; |
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use libvhdl.QueueP.all; |
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use libvhdl.DictP.all; |
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use libvhdl.UtilsP.all; |
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library std; |
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use std.env.all; |
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entity WishBoneT is |
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@ -90,7 +84,6 @@ architecture sim of WishBoneT is |
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); |
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end component WishBoneSlaveE; |
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--* testbench global clock period |
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constant C_PERIOD : time := 5 ns; |
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--* Wishbone data width |
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@ -98,23 +91,26 @@ architecture sim of WishBoneT is |
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--* Wishbone address width |
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constant C_ADDRESS_WIDTH : natural := 8; |
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type t_wishbone is record |
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--+ wishbone outputs |
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Cyc : std_logic; |
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Stb : std_logic; |
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We : std_logic; |
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Adr : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0); |
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WDat : std_logic_vector(C_DATA_WIDTH-1 downto 0); |
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--+ wishbone inputs |
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RDat : std_logic_vector(C_DATA_WIDTH-1 downto 0); |
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Ack : std_logic; |
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Err : std_logic; |
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end record t_wishbone; |
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signal s_wishbone : t_wishbone := ('Z', 'Z', 'Z', (others => 'Z'), (others => 'Z'), (others => 'Z'), 'Z', 'Z'); |
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--* testbench global clock |
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signal s_wb_clk : std_logic := '1'; |
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--* testbench global reset |
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signal s_wb_reset : std_logic := '1'; |
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--+ test done array with entry for each test |
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signal s_test_done : boolean; |
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signal s_wb_cyc : std_logic; |
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signal s_wb_stb : std_logic; |
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signal s_wb_we : std_logic; |
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signal s_wb_adr : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0); |
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signal s_wb_master_data : std_logic_vector(C_DATA_WIDTH-1 downto 0); |
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signal s_wb_slave_data : std_logic_vector(C_DATA_WIDTH-1 downto 0); |
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signal s_wb_ack : std_logic; |
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signal s_wb_err : std_logic; |
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signal s_master_local_wen : std_logic; |
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signal s_master_local_ren : std_logic; |
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signal s_master_local_adress : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0); |
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@ -131,15 +127,23 @@ architecture sim of WishBoneT is |
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type t_register is array (0 to integer'(2**C_ADDRESS_WIDTH-1)) of std_logic_vector(C_DATA_WIDTH-1 downto 0); |
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shared variable sv_wishbone_queue : t_list_queue; |
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shared variable sv_wishbone_dict : t_dict; |
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shared variable sv_coverage : CovPType; |
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package IntSlvDict is new libvhdl.DictP |
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generic map (KEY_TYPE => integer, |
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VALUE_TYPE => std_logic_vector, |
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key_to_string => to_string, |
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value_to_string => to_hstring); |
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shared variable sv_wishbone_dict : IntSlvDict.t_dict; |
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shared variable sv_coverage : CovPType; |
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begin |
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--* testbench global clock |
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s_wb_clk <= not(s_wb_clk) after C_PERIOD/2 when not(s_test_done) else '0'; |
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s_wb_clk <= not(s_wb_clk) after C_PERIOD/2; |
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--* testbench global reset |
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s_wb_reset <= '0' after C_PERIOD * 5; |
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@ -157,7 +161,6 @@ begin |
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variable v_wbmaster_address : integer; |
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variable v_master_local_adress : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0); |
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variable v_wbmaster_data : std_logic_vector(C_DATA_WIDTH-1 downto 0); |
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variable v_error : t_dict_error; |
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begin |
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v_random.InitSeed(v_random'instance_name); |
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v_wbmaster_data := (others => '0'); |
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@ -182,10 +185,7 @@ begin |
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s_master_local_wen <= '0'; |
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wait until rising_edge(s_wb_clk) and s_master_local_ack = '1'; |
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sv_wishbone_queue.push(uint_to_slv(v_wbmaster_address, C_ADDRESS_WIDTH)); |
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sv_wishbone_dict.set(integer'image(v_wbmaster_address), v_wbmaster_data, v_error); |
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assert v_error = NO_ERROR |
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report "ERROR: key error" |
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severity failure; |
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sv_wishbone_dict.set(v_wbmaster_address, v_wbmaster_data); |
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sv_coverage.ICover(v_wbmaster_address); |
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end loop; |
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-- read back and check the wishbone slave registers |
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@ -197,10 +197,7 @@ begin |
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s_master_local_adress <= (others => '0'); |
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s_master_local_ren <= '0'; |
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wait until rising_edge(s_wb_clk) and s_master_local_ack = '1'; |
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sv_wishbone_dict.get(integer'image(slv_to_uint(v_master_local_adress)), v_wbmaster_data, v_error); |
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assert v_error = NO_ERROR |
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report "ERROR: key error" |
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severity failure; |
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sv_wishbone_dict.get(slv_to_uint(v_master_local_adress), v_wbmaster_data); |
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assert_equal(s_master_local_dout, v_wbmaster_data); |
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end loop; |
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-- test local write & read at the same time |
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@ -215,7 +212,7 @@ begin |
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report "INFO: Test successfully finished!"; |
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sv_coverage.SetMessage("WishboneT coverage results"); |
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sv_coverage.WriteBin; |
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s_test_done <= true; |
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finish; |
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wait; |
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end process WbMasterLocalP; |
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@ -230,15 +227,15 @@ begin |
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WbRst_i => s_wb_reset, |
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WbClk_i => s_wb_clk, |
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--+ wishbone outputs |
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WbCyc_o => s_wb_cyc, |
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WbStb_o => s_wb_stb, |
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WbWe_o => s_wb_we, |
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WbAdr_o => s_wb_adr, |
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WbDat_o => s_wb_master_data, |
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WbCyc_o => s_wishbone.Cyc, |
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WbStb_o => s_wishbone.Stb, |
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WbWe_o => s_wishbone.We, |
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WbAdr_o => s_wishbone.Adr, |
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WbDat_o => s_wishbone.WDat, |
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--+ wishbone inputs |
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WbDat_i => s_wb_slave_data, |
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WbAck_i => s_wb_ack, |
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WbErr_i => s_wb_err, |
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WbDat_i => s_wishbone.RDat, |
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WbAck_i => s_wishbone.Ack, |
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WbErr_i => s_wishbone.Err, |
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--+ local register if |
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LocalWen_i => s_master_local_wen, |
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LocalRen_i => s_master_local_ren, |
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@ -258,18 +255,18 @@ begin |
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wait until (s_master_local_wen = '1' or s_master_local_ren = '1') and rising_edge(s_wb_clk); |
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v_master_local_adress := s_master_local_adress; |
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v_master_local_data := s_master_local_din; |
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v_valid_access := s_master_local_wen xor s_master_local_ren; |
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v_valid_access := s_master_local_wen xor s_master_local_ren; |
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wait until rising_edge(s_wb_clk); |
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WB_CYC : assert v_valid_access = s_wb_cyc |
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report "ERROR: Wishbone cycle should be 0b" & to_string(v_valid_access) & " instead of 0b" & to_string(s_wb_cyc) |
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WB_CYC : assert v_valid_access = s_wishbone.Cyc |
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report "ERROR: Wishbone cycle should be 0b" & to_string(v_valid_access) & " instead of 0b" & to_string(s_wishbone.Cyc) |
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severity failure; |
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if (v_valid_access = '1') then |
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WB_ADDR : assert s_wb_adr = v_master_local_adress |
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report "ERROR: Wishbone address 0x" & to_hstring(s_wb_adr) & " differ from local address 0x" & to_hstring(v_master_local_adress) |
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WB_ADDR : assert s_wishbone.Adr = v_master_local_adress |
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report "ERROR: Wishbone address 0x" & to_hstring(s_wishbone.Adr) & " differ from local address 0x" & to_hstring(v_master_local_adress) |
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severity failure; |
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if (s_wb_we = '1') then |
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WB_DATA : assert s_wb_master_data = v_master_local_data |
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report "ERROR: Wishbone data 0x" & to_hstring(s_wb_master_data) & " differ from local data 0x" & to_hstring(v_master_local_data) |
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if (s_wishbone.We = '1') then |
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WB_DATA : assert s_wishbone.WDat = v_master_local_data |
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report "ERROR: Wishbone data 0x" & to_hstring(s_wishbone.WDat) & " differ from local data 0x" & to_hstring(v_master_local_data) |
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severity failure; |
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end if; |
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end if; |
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@ -286,15 +283,15 @@ begin |
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WbRst_i => s_wb_reset, |
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WbClk_i => s_wb_clk, |
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--+ wishbone inputs |
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WbCyc_i => s_wb_cyc, |
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WbStb_i => s_wb_stb, |
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WbWe_i => s_wb_we, |
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WbAdr_i => s_wb_adr, |
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WbDat_i => s_wb_master_data, |
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WbCyc_i => s_wishbone.Cyc, |
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WbStb_i => s_wishbone.Stb, |
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WbWe_i => s_wishbone.We, |
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WbAdr_i => s_wishbone.Adr, |
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WbDat_i => s_wishbone.WDat, |
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--* wishbone outputs |
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WbDat_o => s_wb_slave_data, |
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WbAck_o => s_wb_ack, |
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WbErr_o => s_wb_err, |
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WbDat_o => s_wishbone.RDat, |
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WbAck_o => s_wishbone.Ack, |
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WbErr_o => s_wishbone.Err, |
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--+ local register if |
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LocalWen_o => s_slave_local_wen, |
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LocalRen_o => s_slave_local_ren, |
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