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Add test of stop bit errors

T. Meissner 1 month ago
parent
commit
84d9a28afb
1 changed files with 26 additions and 51 deletions
  1. 26
    51
      test/UartT.vhd

+ 26
- 51
test/UartT.vhd View File

@@ -37,39 +37,6 @@ end entity UartT;
37 37
 architecture sim of UartT is
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39 39
 
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-  component UartTx is
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-    generic (
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-      DATA_LENGTH : positive range 5 to 9 := 8;
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-      PARITY      : boolean := false;
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-      CLK_DIV     : natural := 10
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-    );
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-    port (
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-      reset_n_i   : in  std_logic;                                 -- async reset
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-      clk_i       : in  std_logic;                                 -- clock
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-      data_i      : in  std_logic_vector(DATA_LENGTH-1 downto 0);  -- data input
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-      valid_i     : in  std_logic;                                 -- input data valid
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-      accept_o    : out std_logic;                                 -- inpit data accepted
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-      tx_o        : out std_logic                                  -- uart tx data output
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-    );
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-  end component UartTx;
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-
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-  component UartRx is
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-    generic (
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-      DATA_LENGTH : positive range 5 to 9 := 8;
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-      PARITY      : boolean := true;
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-      CLK_DIV     : natural := 10
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-    );
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-    port (
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-      reset_n_i   : in  std_logic;                                 -- async reset
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-      clk_i       : in  std_logic;                                 -- clock
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-      data_o      : out std_logic_vector(DATA_LENGTH-1 downto 0);  -- data output
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-      error_o     : out std_logic;                                 -- rx error
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-      valid_o     : out std_logic;                                 -- output data valid
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-      accept_i    : in  std_logic;                                 -- output data accepted
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-      rx_i        : in  std_logic                                  -- uart rx input
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-    );
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-  end component UartRx;
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-
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   constant c_data_length : positive range 5 to 9 := 8;
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   constant c_parity      : boolean := true;
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   constant c_clk_div     : natural := 10;
@@ -88,12 +55,13 @@ architecture sim of UartT is
88 55
   signal s_tx_uart   : std_logic := '1';
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   signal s_rx_uart   : std_logic := '1';
90 57
 
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-  signal s_error_inject   : boolean := false;
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-  signal s_error_injected : boolean := false;
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+  type t_error is (NONE, DATA, STOP);
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+  signal s_error_inject   : t_error := NONE;
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+  signal s_error_injected : t_error := NONE;
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   shared variable sv_uart_err_coverage : CovPType;
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-  procedure injectError (signal inject : out boolean) is
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+  procedure injectError (signal inject : out t_error) is
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     variable v_injected : boolean;
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     variable v_random   : RandomPType;
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   begin
@@ -109,17 +77,22 @@ architecture sim of UartT is
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       end loop;
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       -- Possibly distort one of the data bits
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       -- and update coverage object
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-      for i in 0 to c_data_length-1 loop
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+      for i in 0 to c_data_length loop
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         if (not v_injected and v_random.DistValInt(((0, 9), (1, 1))) = 1) then
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           v_injected := true;
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-          inject     <= true;
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           sv_uart_err_coverage.ICover(i);
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-          report "Injected transmit error on bit #" & to_string(i);
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+          if (i = c_data_length) then
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+            inject <= STOP;
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+            report "Injected transmit error on stop bit";
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+          else
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+            inject <= DATA;
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+            report "Injected transmit error on data bit #" & to_string(i);
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+          end if;
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         end if;
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         for y in 0 to c_clk_div-1 loop
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           wait until rising_edge(s_clk);
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         end loop;
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-        inject <= false;
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+        inject <= NONE;
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       end loop;
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     end loop;
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     wait;
@@ -129,7 +102,7 @@ architecture sim of UartT is
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 begin
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131 104
 
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-  Dut_UartTx : UartTx
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+  Dut_UartTx : entity work.UartTx
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     generic map (
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       DATA_LENGTH => c_data_length,
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       PARITY      => c_parity,
@@ -146,12 +119,13 @@ begin
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   -- Error injection based on random
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-  sv_uart_err_coverage.AddBins(GenBin(0, c_data_length-1));
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+  sv_uart_err_coverage.AddBins("DATA_ERROR", GenBin(0, c_data_length-1));
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+  sv_uart_err_coverage.AddBins("STOP_ERROR", GenBin(c_data_length));
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   injectError(s_error_inject);
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-  s_rx_uart <= s_tx_uart when not s_error_inject else not(s_tx_uart);
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+  s_rx_uart <= s_tx_uart when s_error_inject = NONE else not(s_tx_uart);
152 126
 
153 127
 
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-  Dut_UartRx : UartRx
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+  Dut_UartRx : entity work.UartRx
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     generic map (
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       DATA_LENGTH => c_data_length,
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       PARITY      => c_parity,
@@ -173,13 +147,12 @@ begin
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174 148
 
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   -- Store if an error was injected in the current frame
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-  s_error_injected <= true  when rising_edge(s_clk) and s_error_inject else
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-                      false when s_tx_valid = '1';
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+  s_error_injected <= s_error_inject when rising_edge(s_clk) and s_error_inject /= NONE else
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+                      NONE when s_tx_valid = '1';
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179 153
 
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   TestP : process is
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     variable v_data   : std_logic_vector(c_data_length-1 downto 0);
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-    variable v_error  : boolean := false;
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     variable v_random : RandomPType;
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   begin
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     v_random.InitSeed(v_random'instance_name);
@@ -197,10 +170,12 @@ begin
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       wait until rising_edge(s_clk) and s_tx_accept = '1';
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       s_tx_valid <= '0';
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       wait until rising_edge(s_clk) and s_rx_valid = '1';
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-      if s_error_injected then
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-        assert s_rx_data /= v_data
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-          report "Received data 0x" & to_hstring(s_rx_data) & ", expected 0x" & to_hstring(v_data)
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-          severity failure;
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+      if s_error_injected /= NONE then
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+        if s_error_injected = DATA then
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+          assert s_rx_data /= v_data
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+            report "Received data 0x" & to_hstring(s_rx_data) & ", expected 0x" & to_hstring(v_data)
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+            severity failure;
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+        end if;
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         assert s_rx_error = '1'
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           report "Received error 0b" & to_string(s_rx_error) & ", expected 0b1"
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           severity failure;