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@ -3,6 +3,8 @@ library ieee; |
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use ieee.numeric_std.all; |
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--+ including vhdl 2008 libraries |
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--+ These lines can be commented out when using |
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--+ a simulator with built-in VHDL 2008 support |
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library ieee_proposed; |
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use ieee_proposed.standard_additions.all; |
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use ieee_proposed.std_logic_1164_additions.all; |
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@ -49,6 +51,7 @@ begin |
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assert (now - v_time) = C_PERIOD * 20 |
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severity failure; |
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s_tests_done(0) <= true; |
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report "INFO: wait_cycles() procedure tests finished successfully"; |
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wait; |
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end process SimTestP; |
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@ -96,7 +99,7 @@ begin |
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assert_equal(v_master_data, std_logic_vector(to_unsigned(i, 8))); |
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end loop; |
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end loop; |
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report "INFO: SimP tests finished successfully"; |
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report "INFO: spi_* procedures tests finished successfully"; |
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s_tests_done(1) <= true; |
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wait; |
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end process SpiSlaveP; |
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