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@ -108,6 +108,7 @@ architecture sim of UartT is |
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if (not v_injected and v_random.DistValInt(((0, 9), (1, 1))) = 1) then |
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if (not v_injected and v_random.DistValInt(((0, 9), (1, 1))) = 1) then |
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v_injected := true; |
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v_injected := true; |
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inject <= true; |
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inject <= true; |
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report "Injected transmit error on bit #" & to_string(i); |
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end if; |
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end if; |
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for y in 0 to c_clk_div-1 loop |
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for y in 0 to c_clk_div-1 loop |
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wait until rising_edge(s_clk); |
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wait until rising_edge(s_clk); |
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@ -171,7 +172,7 @@ begin |
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TestP : process is |
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TestP : process is |
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variable v_data : std_logic_vector(c_data_length-1 downto 0); |
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variable v_data : std_logic_vector(c_data_length-1 downto 0); |
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variable v_error : boolean := false; |
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variable v_error : boolean := false; |
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variable v_random : RandomPType; |
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variable v_random : RandomPType; |
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begin |
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begin |
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v_random.InitSeed(v_random'instance_name); |
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v_random.InitSeed(v_random'instance_name); |
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@ -185,6 +186,7 @@ begin |
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s_rx_accept <= '1'; |
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s_rx_accept <= '1'; |
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v_data := v_random.RandSlv(8); |
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v_data := v_random.RandSlv(8); |
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s_tx_data <= v_data; |
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s_tx_data <= v_data; |
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report "Testcase #" & to_string(i) & ": Transmit 0x" & to_hstring(v_data); |
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wait until rising_edge(s_clk) and s_tx_accept = '1'; |
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wait until rising_edge(s_clk) and s_tx_accept = '1'; |
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s_tx_valid <= '0'; |
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s_tx_valid <= '0'; |
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wait until rising_edge(s_clk) and s_rx_valid = '1'; |
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wait until rising_edge(s_clk) and s_rx_valid = '1'; |
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