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@ -12,11 +12,13 @@ library ieee; |
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library osvvm; |
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use osvvm.RandomPkg.all; |
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use osvvm.CoveragePkg.all; |
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library libvhdl; |
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use libvhdl.AssertP.all; |
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use libvhdl.SimP.all; |
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use libvhdl.QueueP.all; |
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use libvhdl.DictP.all; |
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use libvhdl.UtilsP.all; |
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@ -129,6 +131,8 @@ architecture sim of WishBoneT is |
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type t_register is array (0 to integer'(2**C_ADDRESS_WIDTH-1)) of std_logic_vector(C_DATA_WIDTH-1 downto 0); |
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shared variable sv_wishbone_queue : t_list_queue; |
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shared variable sv_wishbone_dict : t_dict; |
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shared variable sv_coverage : CovPType; |
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begin |
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@ -143,13 +147,17 @@ begin |
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QueueInitP : process is |
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begin |
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sv_wishbone_queue.init(2**C_ADDRESS_WIDTH); |
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sv_wishbone_dict.init(false); |
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wait; |
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end process QueueInitP; |
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WbMasterLocalP : process is |
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variable v_random : RandomPType; |
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variable v_wbmaster_data : std_logic_vector(C_DATA_WIDTH-1 downto 0); |
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variable v_random : RandomPType; |
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variable v_wbmaster_address : integer; |
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variable v_master_local_adress : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0); |
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variable v_wbmaster_data : std_logic_vector(C_DATA_WIDTH-1 downto 0); |
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variable v_error : t_dict_error; |
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begin |
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v_random.InitSeed(v_random'instance_name); |
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v_wbmaster_data := (others => '0'); |
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@ -159,30 +167,45 @@ begin |
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s_master_local_ren <= '0'; |
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wait until s_wb_reset = '0'; |
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-- write the wishbone slave registers |
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for i in 0 to integer'(2**C_ADDRESS_WIDTH-1) loop |
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sv_coverage.AddBins(GenBin(0)); |
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sv_coverage.AddBins(GenBin(integer'(2**C_ADDRESS_WIDTH-1))); |
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sv_coverage.AddBins(GenBin(1, integer'(2**C_ADDRESS_WIDTH-2), 64)); |
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while not sv_coverage.IsCovered loop |
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v_wbmaster_address := sv_coverage.RandCovPoint; |
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v_wbmaster_data := v_random.RandSlv(C_DATA_WIDTH); |
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s_master_local_din <= v_wbmaster_data; |
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s_master_local_adress <= uint_to_slv(i, C_ADDRESS_WIDTH); |
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s_master_local_adress <= uint_to_slv(v_wbmaster_address, C_ADDRESS_WIDTH); |
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s_master_local_wen <= '1'; |
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wait until rising_edge(s_wb_clk); |
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s_master_local_din <= (others => '0'); |
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s_master_local_adress <= (others => '0'); |
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s_master_local_wen <= '0'; |
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wait until rising_edge(s_wb_clk) and s_master_local_ack = '1'; |
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sv_wishbone_queue.push(v_wbmaster_data); |
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sv_wishbone_queue.push(uint_to_slv(v_wbmaster_address, C_ADDRESS_WIDTH)); |
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sv_wishbone_dict.set(integer'image(v_wbmaster_address), v_wbmaster_data, v_error); |
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assert v_error = NO_ERROR |
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report "ERROR: key error" |
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severity failure; |
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sv_coverage.ICover(v_wbmaster_address); |
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end loop; |
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-- read back and check the wishbone slave registers |
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for i in 0 to integer'(2**C_ADDRESS_WIDTH-1) loop |
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s_master_local_adress <= uint_to_slv(i, C_ADDRESS_WIDTH); |
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while not(sv_wishbone_queue.is_empty) loop |
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sv_wishbone_queue.pop(v_master_local_adress); |
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s_master_local_adress <= v_master_local_adress; |
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s_master_local_ren <= '1'; |
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wait until rising_edge(s_wb_clk); |
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s_master_local_adress <= (others => '0'); |
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s_master_local_ren <= '0'; |
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wait until rising_edge(s_wb_clk) and s_master_local_ack = '1'; |
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sv_wishbone_queue.pop(v_wbmaster_data); |
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sv_wishbone_dict.get(integer'image(slv_to_uint(v_master_local_adress)), v_wbmaster_data, v_error); |
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assert v_error = NO_ERROR |
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report "ERROR: key error" |
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severity failure; |
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assert_equal(s_master_local_dout, v_wbmaster_data); |
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end loop; |
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report "INFO: Test successfully finished!"; |
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sv_coverage.SetMessage("WishboneT coverage results"); |
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sv_coverage.WriteBin; |
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s_test_done <= true; |
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wait; |
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end process WbMasterLocalP; |
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