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New Wishbone checks; Fix illegal PSL property

* A lot of new checks are added to WishboneCheckerE unit
  trying to implement the rules of the Wishbone spec.
* An illegal use of the suffix implication instead of logical
  implicationis fixed in WishboneMasterE unit
T. Meissner 3 months ago
parent
commit
dd494f0901
5 changed files with 53 additions and 10 deletions
  1. 46
    3
      syn/WishBoneCheckerE.vhd
  2. 1
    1
      syn/WishBoneMasterE.vhd
  3. 2
    1
      syn/WishBoneP.vhd
  4. 1
    1
      test/Makefile
  5. 3
    4
      test/WishBoneT.vhd

+ 46
- 3
syn/WishBoneCheckerE.vhd View File

@@ -18,7 +18,8 @@ entity WishBoneCheckerE is
18 18
     --+ wishbone inputs
19 19
     WbSDat_i      : in std_logic_vector;
20 20
     WbSAck_i      : in std_logic;
21
-    WbSErr_i      : in std_logic
21
+    WbSErr_i      : in std_logic;
22
+    WbRty_i       : in std_logic
22 23
   );
23 24
 end entity WishBoneCheckerE;
24 25
 
@@ -33,10 +34,10 @@ begin
33 34
   --
34 35
   -- Wishbone protocol checks
35 36
   --
36
-  -- psl property initialize(boolean init_state) is
37
+  -- psl property initialize_interface (boolean init_state) is
37 38
   --   always ({WbRst_i} |=> {init_state[+] && {WbRst_i[*]; not(WbRst_i)}});
38 39
   --
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-  -- psl RULE_3_00 : assert initialize(not(WbMCyc_i) and not(WbMStb_i) and not(WbMWe_i))
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+  -- psl RULE_3_00 : assert initialize_interface (not(WbMCyc_i) and not(WbMStb_i) and not(WbMWe_i))
40 41
   --   report "Wishbone rule 3.00 violated";
41 42
   --
42 43
   -- psl property reset_signal is
@@ -45,11 +46,48 @@ begin
45 46
   -- psl RULE_3_05 : assert reset_signal
46 47
   --   report "Wishbone rule 3.05 violated";
47 48
   --
49
+  -- psl property CYC_O_signal is
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+  --   always {not(WbMStb_i); WbMStb_i} |-> {(WbMCyc_i and WbMStb_i)[+]; not(WbMStb_i)};
51
+  --
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+  -- psl RULE_3_25 : assert CYC_O_signal
53
+  --   report "Wishbone rule 3.25 violated";
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+  --
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+  -- psl property slave_no_response is
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+  --   always not(WbMCyc_i) -> not(WbSAck_i) and not(WbSErr_i);
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+  --
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+  -- psl property slave_response_to_master is
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+  --  always {not(WbMStb_i); WbMStb_i} |->
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+  --         {{(WbMStb_i and not(WbSAck_i))[*];
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+  --           WbMStb_i and WbSAck_i;
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+  --           not(WbMStb_i)} |
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+  --          {(WbMStb_i and not(WbSErr_i))[*];
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+  --           WbMStb_i and WbSErr_i;
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+  --           not(WbMStb_i)} |
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+  --          {(WbMStb_i and not(WbRty_i))[*];
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+  --           WbMStb_i and WbRty_i;
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+  --           not(WbMStb_i)}
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+  -- };
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+  --
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+  -- psl RULE_3_30_0 : assert slave_no_response
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+  --   report "Wishbone rule 3.30_0 violated";
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+  --
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+  -- psl RULE_3_30_1 : assert slave_response_to_master
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+  --   report "Wishbone rule 3.30_0 violated";
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+  --
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+  -- psl property slave_response is 
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+  --   always {not(WbMStb_i); WbMCyc_i and WbMStb_i} |->
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+  --     {not(WbSAck_i or WbSErr_i or WbRty_i)[*]; WbSAck_i or WbSErr_i or WbRty_i};
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+  --
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+  -- psl RULE_3_35 : assert slave_response
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+  --   report "Wishbone rule 3.35 violated";
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+  --
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+  -- psl property response_signals is
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+  --   never ((WbSErr_i and WbRty_i) or (WbSErr_i and WbSAck_i) or (WbSAck_i and WbRty_i));
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+  --
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+  -- psl RULE_3_45 : assert response_signals
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+  --   report "Wishbone rule 3.45 violated";
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+  --
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+  -- -- psl property slave_negated_response is
48 91
 
49 92
 
50 93
 end architecture check;

+ 1
- 1
syn/WishBoneMasterE.vhd View File

@@ -129,7 +129,7 @@ begin
129 129
   --   report "WB master: Write error";
130 130
   --
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   -- psl WB_READ : assert always
132
-  --   ((not(WbCyc_o) and not(WbStb_o) and LocalRen_i and not(LocalWen_i)) |->
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+  --   ((not(WbCyc_o) and not(WbStb_o) and LocalRen_i and not(LocalWen_i)) ->
133 133
   --    next (WbCyc_o = '1' and WbStb_o = '1' and WbWe_o = '0')) abort WbRst_i
134 134
   --   report "WB master: Read error";
135 135
 

+ 2
- 1
syn/WishBoneP.vhd View File

@@ -73,7 +73,8 @@ package WishBoneP is
73 73
       --+ wishbone inputs
74 74
       WbSDat_i      : in std_logic_vector;
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       WbSAck_i      : in std_logic;
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-      WbSErr_i      : in std_logic
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+      WbSErr_i      : in std_logic;
77
+      WbRty_i       : in std_logic
77 78
     );
78 79
   end component WishBoneCheckerE;
79 80
 

+ 1
- 1
test/Makefile View File

@@ -68,7 +68,7 @@ spi: spit
68 68
 	ghdl -r --std=$(VHD_STD) $@t --wave=$@t.ghw
69 69
 
70 70
 
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-wishbonet: OsvvmContext.o AssertP.o SimP.o QueueP.o DictP.o UtilsP.o \
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+wishbonet: OsvvmContext.o AssertP.o SimP.o QueueP.o DictP.o UtilsP.o $(SYN_SRC)/WishBoneCheckerE.vhd \
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 	  $(SYN_SRC)/WishBoneP.vhd $(SYN_SRC)/WishBoneMasterE.vhd $(SYN_SRC)/WishBoneSlaveE.vhd WishBoneT.vhd
73 73
 	ghdl -a --std=$(VHD_STD) -fpsl $(SYN_SRC)/WishBoneP.vhd
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 	ghdl -a --std=$(VHD_STD) -fpsl $(SYN_SRC)/WishBoneCheckerE.vhd $(SYN_SRC)/WishBoneMasterE.vhd $(SYN_SRC)/WishBoneSlaveE.vhd

+ 3
- 4
test/WishBoneT.vhd View File

@@ -236,7 +236,6 @@ begin
236 236
 
237 237
 
238 238
   WbSlaveLocalP : process is
239
-    variable v_data : std_logic_vector(s_slave_local_din'range);
240 239
   begin
241 240
     wait until rising_edge(s_wb_clk);
242 241
     if (s_wb_reset = '1') then
@@ -248,8 +247,7 @@ begin
248 247
         WB_SLAVE_REG : assert sv_wb_slave_dict.hasKey(slv_to_uint(s_slave_local_adress))
249 248
           report "ERROR: Requested register at addr 0x" & to_hstring(s_slave_local_adress) & " not written before"
250 249
           severity failure;
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-        sv_wb_slave_dict.get(slv_to_uint(s_slave_local_adress), v_data);
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-        s_slave_local_din <= v_data;
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+        s_slave_local_din <= sv_wb_slave_dict.get(slv_to_uint(s_slave_local_adress));
253 251
       end if;
254 252
     end if;
255 253
   end process WbSlaveLocalP;
@@ -269,7 +267,8 @@ i_WishBoneChecker : WishBoneCheckerE
269 267
     --+ wishbone inputs
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     WbSDat_i      => s_wishbone.RDat,
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     WbSAck_i      => s_wishbone.Ack,
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-    WbSErr_i      => s_wishbone.Err
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+    WbSErr_i      => s_wishbone.Err,
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+    WbRty_i       => '0'
273 272
   );
274 273
 
275 274