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tmeissner
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libvhdl
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Library of reusable VHDL components
vhdl
ghdl
osvvm
psl
fpga
testbenches
coverage
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77
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914 KiB
VHDL
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T. Meissner
021bab3762
Add PSL assertions to check WishBone & Local IF
Various new PSL assertions to check ports during Wishbone write & read transfer and reset state
9 years ago
..
SpiMasterE.vhd
ste is now generated combinatoral in parallel to the fsm
10 years ago
SpiSlaveE.vhd
add generic G_DATA_DIR to set if we want transfer from LSB to MSB ore vice versa
10 years ago
WishBoneMasterE.vhd
react to slave ack in ADDRESS state
10 years ago
WishBoneSlaveE.vhd
Add PSL assertions to check WishBone & Local IF
9 years ago