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132 lines
3.8 KiB
132 lines
3.8 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity WishBoneMasterE is
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generic (
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G_ADR_WIDTH : positive := 8; --* address bus width
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G_DATA_WIDTH : positive := 8 --* data bus width
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);
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port (
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--+ wishbone system if
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WbRst_i : in std_logic;
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WbClk_i : in std_logic;
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--+ wishbone outputs
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WbCyc_o : out std_logic;
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WbStb_o : out std_logic;
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WbWe_o : out std_logic;
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WbAdr_o : out std_logic_vector(G_ADR_WIDTH-1 downto 0);
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WbDat_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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--+ wishbone inputs
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WbDat_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
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WbAck_i : in std_logic;
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WbErr_i : in std_logic;
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--+ local register if
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LocalWen_i : in std_logic;
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LocalRen_i : in std_logic;
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LocalAdress_i : in std_logic_vector(G_ADR_WIDTH-1 downto 0);
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LocalData_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
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LocalData_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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LocalAck_o : out std_logic;
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LocalError_o : out std_logic
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);
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end entity WishBoneMasterE;
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architecture rtl of WishBoneMasterE is
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type t_wb_master_fsm is (IDLE, ADDRESS, DATA);
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signal s_wb_master_fsm : t_wb_master_fsm;
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signal s_wb_wen : std_logic;
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begin
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--+ Wishbone master control state machine
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WbMasterStatesP : process (WbClk_i) is
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begin
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if (rising_edge(WbClk_i)) then
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if (WbRst_i = '1') then
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s_wb_master_fsm <= IDLE;
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else
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WbReadC : case s_wb_master_fsm is
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when IDLE =>
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if (LocalWen_i = '1' or LocalRen_i = '1') then
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s_wb_master_fsm <= ADDRESS;
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end if;
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when ADDRESS =>
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if (WbAck_i = '1' or WbErr_i = '1') then
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s_wb_master_fsm <= IDLE;
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else
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s_wb_master_fsm <= DATA;
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end if;
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when DATA =>
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if (WbErr_i = '1' or WbAck_i = '1') then
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s_wb_master_fsm <= IDLE;
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end if;
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when others =>
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s_wb_master_fsm <= IDLE;
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end case;
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end if;
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end if;
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end process WbMasterStatesP;
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--+ combinatoral local register if outputs
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LocalData_o <= WbDat_i when s_wb_master_fsm = DATA else (others => '0');
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LocalError_o <= WbErr_i when s_wb_master_fsm /= IDLE else '0';
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LocalAck_o <= WbAck_i when (s_wb_master_fsm = ADDRESS or s_wb_master_fsm = DATA) and WbErr_i = '0' else '0';
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--+ combinatoral wishbone if outputs
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WbStb_o <= '1' when s_wb_master_fsm /= IDLE else '0';
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WbCyc_o <= '1' when s_wb_master_fsm /= IDLE else '0';
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WbWe_o <= s_wb_wen when s_wb_master_fsm /= IDLE else '0';
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--+ registered wishbone if outputs
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OutRegsP : process (WbClk_i) is
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begin
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if(rising_edge(WbClk_i)) then
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if(WbRst_i = '1') then
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WbAdr_o <= (others => '0');
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WbDat_o <= (others => '0');
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s_wb_wen <= '0';
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else
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if (s_wb_master_fsm = IDLE) then
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if (LocalWen_i = '1' or LocalRen_i = '1') then
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WbAdr_o <= LocalAdress_i;
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s_wb_wen <= LocalWen_i;
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end if;
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if (LocalWen_i = '1') then
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WbDat_o <= LocalData_i;
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end if;
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end if;
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end if;
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end if;
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end process OutRegsP;
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-- psl default clock is rising_edge(WbClk_i);
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--
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-- psl WB_WRITE : assert always
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-- ((not(WbCyc_o) and not(WbStb_o) and LocalWen_i) ->
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-- next (WbCyc_o = '1' and WbStb_o = '1' and WbWe_o = '1')) abort WbRst_i
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-- report "PSL ERROR: Wishbone write error";
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--
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-- psl WB_READ : assert always
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-- ((not(WbCyc_o) and not(WbStb_o) and LocalRen_i) |->
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-- next (WbCyc_o = '1' and WbStb_o = '1' and WbWe_o = '0')) abort WbRst_i
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-- report "PSL ERROR: Wishbone read error";
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end architecture rtl;
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