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69 lines
1.6 KiB
69 lines
1.6 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--+ including vhdl 2008 libraries
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--+ These lines can be commented out when using
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--+ a simulator with built-in VHDL 2008 support
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--library ieee_proposed;
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-- use ieee_proposed.standard_additions.all;
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-- use ieee_proposed.std_logic_1164_additions.all;
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-- use ieee_proposed.numeric_std_additions.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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library libvhdl;
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use libvhdl.AssertP.all;
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use libvhdl.StackP.all;
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entity StackT is
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end entity StackT;
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architecture sim of StackT is
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constant C_STACK_DEPTH : natural := 64;
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type t_scoreboard is array (natural range <>) of std_logic_vector(7 downto 0);
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shared variable sv_stack : t_stack;
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begin
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StackInitP : process is
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begin
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sv_stack.init(false);
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wait;
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end process StackInitP;
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StackTestP : process is
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variable v_data : std_logic_vector(7 downto 0);
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begin
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-- check initial emptiness
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assert_true(sv_stack.is_empty, "Stack should be empty!");
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for i in 0 to C_STACK_DEPTH-1 loop
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sv_stack.push(std_logic_vector(to_unsigned(i, 8)));
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end loop;
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-- check that it's full
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assert_equal(sv_stack.fillstate, C_STACK_DEPTH, "Stack should have" & integer'image(C_STACK_DEPTH) & "entries");
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-- empty the queue
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for i in C_STACK_DEPTH-1 downto 0 loop
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sv_stack.pop(v_data);
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assert_equal(v_data, std_logic_vector(to_unsigned(i, 8)));
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end loop;
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-- check emptiness
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assert_true(sv_stack.is_empty, "Stack should be empty!");
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report "INFO: t_stack test finished successfully";
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wait;
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end process StackTestP;
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end architecture sim;
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