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Library of reusable VHDL components
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libvhdl/syn
T. Meissner f0e490142e moved register write into ADDRESS state, decreasing the write to one cycle only 11 years ago
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SpiMasterE.vhd ste is now generated combinatoral in parallel to the fsm 11 years ago
SpiSlaveE.vhd add generic G_DATA_DIR to set if we want transfer from LSB to MSB ore vice versa 11 years ago
WishBoneMasterE.vhd react to slave ack in ADDRESS state 11 years ago
WishBoneSlaveE.vhd moved register write into ADDRESS state, decreasing the write to one cycle only 11 years ago