Library of reusable VHDL components
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T. Meissner c1005badfc Add PSL assertions to check initiating of WishBone write/read transfer 9 years ago
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SpiMasterE.vhd ste is now generated combinatoral in parallel to the fsm 10 years ago
SpiSlaveE.vhd add generic G_DATA_DIR to set if we want transfer from LSB to MSB ore vice versa 10 years ago
WishBoneMasterE.vhd Add PSL assertions to check initiating of WishBone write/read transfer 9 years ago
WishBoneSlaveE.vhd Fix PSL assertions for local wen and local ren 9 years ago