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110 lines
3.6 KiB
110 lines
3.6 KiB
library ieee;
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use ieee.std_logic_1164.all;
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library libvhdl;
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use libvhdl.AssertP.all;
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package SimP is
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procedure wait_cycles (signal clk : in std_logic; n : in natural);
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procedure spi_master ( data_in : in std_logic_vector; data_out : out std_logic_vector;
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signal sclk : inout std_logic; signal ste : out std_logic;
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signal mosi : out std_logic; signal miso : in std_logic;
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cpol : in natural range 0 to 1; cpha : in natural range 0 to 1;
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period : in time);
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procedure spi_slave ( data_in : in std_logic_vector; data_out : out std_logic_vector;
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signal sclk : in std_logic; signal ste : in std_logic;
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signal mosi : in std_logic; signal miso : out std_logic;
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cpol : in natural range 0 to 1; cpha : in natural range 0 to 1);
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end package SimP;
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package body SimP is
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-- wait for n rising edges on clk
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procedure wait_cycles (signal clk : in std_logic; n : in natural) is
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begin
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for i in 1 to n loop
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wait until rising_edge(clk);
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end loop;
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end procedure wait_cycles;
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-- configurable spi master which supports all combinations of cpol & cpha
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procedure spi_master ( data_in : in std_logic_vector; data_out : out std_logic_vector;
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signal sclk : inout std_logic; signal ste : out std_logic;
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signal mosi : out std_logic; signal miso : in std_logic;
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cpol : in natural range 0 to 1; cpha : in natural range 0 to 1;
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period : in time) is
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begin
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assert_equal(data_in'length, data_out'length, "data_in & data_out must have same length!");
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sclk <= std_logic'val(cpol+2);
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ste <= '0';
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if (cpha = 0) then
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for i in data_in'range loop
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mosi <= data_in(i);
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wait for period;
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sclk <= not(sclk);
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data_out(i) := miso;
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wait for period;
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sclk <= not(sclk);
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end loop;
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wait for period;
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else
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mosi <= '1';
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wait for period;
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for i in data_in'range loop
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sclk <= not(sclk);
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mosi <= data_in(i);
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wait for period;
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sclk <= not(sclk);
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data_out(i) := miso;
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wait for period;
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end loop;
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end if;
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ste <= '1';
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mosi <= '1';
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wait for period;
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end procedure spi_master;
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-- configurable spi slave which supports all combinations of cpol & cpha
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procedure spi_slave ( data_in : in std_logic_vector; data_out : out std_logic_vector;
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signal sclk : in std_logic; signal ste : in std_logic;
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signal mosi : in std_logic; signal miso : out std_logic;
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cpol : in natural range 0 to 1; cpha : in natural range 0 to 1) is
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variable v_cpol : std_logic := std_logic'val(cpol+2);
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begin
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assert_equal(data_in'length, data_out'length, "data_in & data_out must have same length!");
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miso <= 'Z';
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wait until ste = '0';
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if (cpha = 0) then
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for i in data_in'range loop
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miso <= data_in(i);
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wait until sclk'event and sclk = not(v_cpol);
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data_out(i) := mosi;
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wait until sclk'event and sclk = v_cpol;
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end loop;
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else
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for i in data_in'range loop
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wait until sclk'event and sclk = not(v_cpol);
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miso <= data_in(i);
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wait until sclk'event and sclk = v_cpol;
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data_out(i) := mosi;
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end loop;
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end if;
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wait until ste = '1';
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miso <= 'Z';
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end procedure spi_slave;
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end package body SimP;
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