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153 lines
4.0 KiB
153 lines
4.0 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library libvhdl;
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use libvhdl.StringP.all;
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use libvhdl.AssertP.all;
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use libvhdl.SimP.all;
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entity SpiT is
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end entity SpiT;
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architecture sim of SpiT is
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component SpiSlaveE is
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generic (
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G_DATA_WIDTH : positive := 8;
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G_SPI_CPOL : natural range 0 to 1 := 0;
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G_SPI_CPHA : natural range 0 to 1 := 0
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);
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port (
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--+ system if
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Reset_n_i : in std_logic;
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Clk_i : in std_logic;
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--+ SPI slave if
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SpiSclk_i : in std_logic;
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SpiSte_i : in std_logic;
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SpiMosi_i : in std_logic;
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SpiMiso_o : out std_logic;
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--+ local VAI if
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Data_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
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DataValid_i : in std_logic;
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DataAccept_o : out std_logic;
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Data_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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DataValid_o : out std_logic;
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DataAccept_i : in std_logic
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);
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end component SpiSlaveE;
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constant C_PERIOD : time := 5 ns;
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constant C_DATA_WIDTH : natural := 8;
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signal s_done : boolean := false;
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signal s_clk : std_logic := '0';
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signal s_reset_n : std_logic := '0';
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signal s_sclk : std_logic;
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signal s_ste : std_logic;
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signal s_mosi : std_logic;
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signal s_miso : std_logic;
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subtype t_spi_mode is natural range 0 to 3;
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signal s_spi_mode : t_spi_mode;
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begin
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s_clk <= not(s_clk) after C_PERIOD when not(s_done) else '0';
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s_reset_n <= '1' after 100 ns;
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-- Unit test of spi master procedure, checks all combinations
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-- of cpol & cpha against spi slave procedure
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SpiMasterP : process is
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variable v_slave_data : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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begin
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s_sclk <= '1';
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s_ste <= '1';
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s_mosi <= '1';
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s_spi_mode <= 0;
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wait until s_reset_n = '1';
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for mode in 0 to 3 loop
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s_spi_mode <= mode;
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for i in 0 to integer'(2**C_DATA_WIDTH-1) loop
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spi_master (data_in => std_logic_vector(to_unsigned(i, C_DATA_WIDTH)),
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data_out => v_slave_data,
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sclk => s_sclk,
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ste => s_ste,
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mosi => s_mosi,
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miso => s_miso,
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cpol => mode / 2,
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cpha => mode mod 2,
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period => 1 us
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);
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assert_equal(v_slave_data, std_logic_vector(to_unsigned(i, C_DATA_WIDTH)));
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end loop;
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report "INFO: SPI mode " & integer'image(mode) & " test successfully";
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end loop;
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report "INFO: SpiSlaveE tests finished successfully";
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s_done <= true;
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wait;
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end process SpiMasterP;
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--+ spi ste demultiplexing
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SpiSlavesG : for mode in t_spi_mode'low to t_spi_mode'high generate
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subtype t_control_array is std_logic_vector(t_spi_mode'low to t_spi_mode'high);
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signal s_spislave_ste : t_control_array;
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type t_data_array is array (t_spi_mode'low to t_spi_mode'high) of std_logic_vector(C_DATA_WIDTH-1 downto 0);
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signal s_din : t_data_array;
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signal s_dout : t_data_array;
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signal s_dout_valid : t_control_array;
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signal s_dout_accept : t_control_array;
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begin
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s_din(mode) <= std_logic_vector(unsigned(s_dout(mode)) + 1);
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s_spislave_ste(mode) <= s_ste when s_spi_mode = mode else '1';
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i0_SpiSlaveE : SpiSlaveE
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generic map (
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G_DATA_WIDTH => 8,
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G_SPI_CPOL => mode / 2,
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G_SPI_CPHA => mode mod 2
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)
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port map (
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--+ system if
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Reset_n_i => s_reset_n,
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Clk_i => s_clk,
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--+ SPI slave if
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SpiSclk_i => s_sclk,
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SpiSte_i => s_spislave_ste(mode),
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SpiMosi_i => s_mosi,
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SpiMiso_o => s_miso,
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--+ local VAI if
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Data_i => s_din(mode),
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DataValid_i => s_dout_valid(mode),
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DataAccept_o => s_dout_accept(mode),
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Data_o => s_dout(mode),
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DataValid_o => s_dout_valid(mode),
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DataAccept_i => s_dout_accept(mode)
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);
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end generate SpiSlavesG;
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end architecture sim;
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