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158 lines
4.9 KiB
158 lines
4.9 KiB
-- ======================================================================
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-- UART testbench
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-- Copyright (C) 2020 Torsten Meissner
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-------------------------------------------------------------------------
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-- This program is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 3 of the License, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with this program; if not, write to the Free Software Foundation,
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-- Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-- ======================================================================
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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use std.env.all;
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entity UartT is
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end entity UartT;
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architecture sim of UartT is
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component UartTx is
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generic (
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DATA_LENGTH : positive range 5 to 9 := 8;
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PARITY : boolean := false;
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CLK_DIV : natural := 10
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);
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port (
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reset_n_i : in std_logic; -- async reset
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clk_i : in std_logic; -- clock
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data_i : in std_logic_vector(DATA_LENGTH-1 downto 0); -- data input
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valid_i : in std_logic; -- input data valid
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accept_o : out std_logic; -- inpit data accepted
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tx_o : out std_logic -- uart tx data output
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);
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end component UartTx;
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component UartRx is
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generic (
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DATA_LENGTH : positive range 5 to 9 := 8;
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PARITY : boolean := true;
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CLK_DIV : natural := 10
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);
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port (
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reset_n_i : in std_logic; -- async reset
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clk_i : in std_logic; -- clock
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data_o : out std_logic_vector(DATA_LENGTH-1 downto 0); -- data output
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error_o : out std_logic; -- rx error
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valid_o : out std_logic; -- output data valid
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accept_i : in std_logic; -- output data accepted
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rx_i : in std_logic -- uart rx input
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);
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end component UartRx;
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constant c_data_length : positive range 5 to 8 := 8;
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signal s_reset_n : std_logic := '0';
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signal s_clk : std_logic := '1';
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signal s_tx_data : std_logic_vector(c_data_length-1 downto 0);
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signal s_tx_valid : std_logic;
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signal s_tx_accept : std_logic;
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signal s_rx_data : std_logic_vector(c_data_length-1 downto 0);
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signal s_rx_error : std_logic;
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signal s_rx_valid : std_logic;
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signal s_rx_accept : std_logic;
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signal s_uart : std_logic;
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begin
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Dut_UartTx : UartTx
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generic map (
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DATA_LENGTH => c_data_length,
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PARITY => true,
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CLK_DIV => 10
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)
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port map (
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reset_n_i => s_reset_n,
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clk_i => s_clk,
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data_i => s_tx_data,
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valid_i => s_tx_valid,
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accept_o => s_tx_accept,
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tx_o => s_uart
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);
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Dut_UartRx : UartRx
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generic map (
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DATA_LENGTH => c_data_length,
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PARITY => true,
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CLK_DIV => 10
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)
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port map (
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reset_n_i => s_reset_n,
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clk_i => s_clk,
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data_o => s_rx_data,
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error_o => s_rx_error,
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valid_o => s_rx_valid,
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accept_i => s_rx_accept,
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rx_i => s_uart
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);
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s_clk <= not s_clk after 5 ns;
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s_reset_n <= '1' after 20 ns;
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TestP : process is
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variable v_data : std_logic_vector(c_data_length-1 downto 0);
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variable v_random : RandomPType;
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begin
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v_random.InitSeed(v_random'instance_name);
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s_tx_valid <= '0';
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s_rx_accept <= '0';
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s_tx_data <= (others => '0');
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wait until s_reset_n = '1';
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for i in 0 to 2**c_data_length-1 loop
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wait until rising_edge(s_clk);
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s_tx_valid <= '1';
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s_rx_accept <= '1';
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v_data := v_random.RandSlv(8);
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s_tx_data <= v_data;
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wait until rising_edge(s_clk) and s_tx_accept = '1';
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s_tx_valid <= '0';
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wait until rising_edge(s_clk) and s_rx_valid = '1';
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assert s_rx_data = v_data
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report "Received data 0x" & to_hstring(s_rx_data) & ", expected 0x" & to_hstring(v_data)
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severity failure;
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assert s_rx_error = '0'
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report "Received error 0b" & to_string(s_rx_error) & ", expected 0b0"
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severity failure;
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end loop;
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wait for 10 us;
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stop(0);
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end process TestP;
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end architecture sim;
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