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266 lines
8.8 KiB
266 lines
8.8 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--+ including vhdl 2008 libraries
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--+ These lines can be commented out when using
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--+ a simulator with built-in VHDL 2008 support
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library ieee_proposed;
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use ieee_proposed.standard_additions.all;
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use ieee_proposed.std_logic_1164_additions.all;
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use ieee_proposed.numeric_std_additions.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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library libvhdl;
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use libvhdl.AssertP.all;
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use libvhdl.SimP.all;
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use libvhdl.QueueP.all;
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entity WishBoneT is
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end entity WishBoneT;
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architecture sim of WishBoneT is
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component WishBoneMasterE is
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generic (
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G_ADR_WIDTH : positive := 8; --* address bus width
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G_DATA_WIDTH : positive := 8 --* data bus width
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);
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port (
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--+ wishbone system if
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WbRst_i : in std_logic;
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WbClk_i : in std_logic;
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--+ wishbone outputs
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WbCyc_o : out std_logic;
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WbStb_o : out std_logic;
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WbWe_o : out std_logic;
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WbAdr_o : out std_logic_vector(G_ADR_WIDTH-1 downto 0);
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WbDat_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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--+ wishbone inputs
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WbDat_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
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WbAck_i : in std_logic;
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WbErr_i : in std_logic;
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--+ local register if
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LocalWen_i : in std_logic;
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LocalRen_i : in std_logic;
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LocalAdress_i : in std_logic_vector(G_ADR_WIDTH-1 downto 0);
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LocalData_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
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LocalData_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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LocalAck_o : out std_logic;
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LocalError_o : out std_logic
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);
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end component WishBoneMasterE;
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component WishBoneSlaveE is
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generic (
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G_ADR_WIDTH : positive := 8; --* address bus width
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G_DATA_WIDTH : positive := 8 --* data bus width
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);
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port (
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--+ wishbone system if
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WbRst_i : in std_logic;
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WbClk_i : in std_logic;
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--+ wishbone inputs
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WbCyc_i : in std_logic;
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WbStb_i : in std_logic;
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WbWe_i : in std_logic;
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WbAdr_i : in std_logic_vector(G_ADR_WIDTH-1 downto 0);
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WbDat_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
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--* wishbone outputs
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WbDat_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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WbAck_o : out std_logic;
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WbErr_o : out std_logic;
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--+ local register if
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LocalWen_o : out std_logic;
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LocalRen_o : out std_logic;
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LocalAdress_o : out std_logic_vector(G_ADR_WIDTH-1 downto 0);
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LocalData_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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LocalData_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0)
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);
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end component WishBoneSlaveE;
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--* testbench global clock period
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constant C_PERIOD : time := 5 ns;
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--* Wishbone data width
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constant C_DATA_WIDTH : natural := 8;
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--* Wishbone address width
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constant C_ADDRESS_WIDTH : natural := 8;
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--* testbench global clock
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signal s_wb_clk : std_logic := '1';
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--* testbench global reset
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signal s_wb_reset : std_logic := '1';
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--+ test done array with entry for each test
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signal s_test_done : boolean;
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signal s_wb_cyc : std_logic;
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signal s_wb_stb : std_logic;
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signal s_wb_we : std_logic;
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signal s_wb_adr : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0);
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signal s_wb_master_data : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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signal s_wb_slave_data : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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signal s_wb_ack : std_logic;
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signal s_wb_err : std_logic;
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signal s_master_local_wen : std_logic;
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signal s_master_local_ren : std_logic;
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signal s_master_local_adress : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0);
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signal s_master_local_din : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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signal s_master_local_dout : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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signal s_master_local_ack : std_logic;
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signal s_master_local_error : std_logic;
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signal s_slave_local_wen : std_logic;
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signal s_slave_local_ren : std_logic;
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signal s_slave_local_adress : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0);
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signal s_slave_local_dout : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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signal s_slave_local_din : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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type t_register is array (0 to integer'(2**C_ADDRESS_WIDTH-1)) of std_logic_vector(C_DATA_WIDTH-1 downto 0);
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shared variable sv_wishbone_queue : t_list_queue;
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begin
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--* testbench global clock
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s_wb_clk <= not(s_wb_clk) after C_PERIOD/2 when not(s_test_done) else '0';
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--* testbench global reset
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s_wb_reset <= '0' after C_PERIOD * 5;
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QueueInitP : process is
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begin
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sv_wishbone_queue.init(2**C_ADDRESS_WIDTH);
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wait;
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end process QueueInitP;
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WbMasterLocalP : process is
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variable v_random : RandomPType;
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variable v_wbmaster_data : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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begin
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v_random.InitSeed(v_random'instance_name);
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v_wbmaster_data := (others => '0');
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s_master_local_din <= (others => '0');
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s_master_local_adress <= (others => '0');
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s_master_local_wen <= '0';
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s_master_local_ren <= '0';
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wait until s_wb_reset = '0';
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-- write the wishbone slave registers
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for i in 0 to integer'(2**C_ADDRESS_WIDTH-1) loop
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v_wbmaster_data := v_random.RandSlv(C_DATA_WIDTH);
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s_master_local_din <= v_wbmaster_data;
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s_master_local_adress <= std_logic_vector(to_unsigned(i, C_ADDRESS_WIDTH));
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s_master_local_wen <= '1';
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wait until rising_edge(s_wb_clk);
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s_master_local_din <= (others => '0');
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s_master_local_adress <= (others => '0');
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s_master_local_wen <= '0';
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wait until rising_edge(s_wb_clk) and s_master_local_ack = '1';
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sv_wishbone_queue.push(v_wbmaster_data);
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end loop;
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-- read back and check the wishbone slave registers
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for i in 0 to integer'(2**C_ADDRESS_WIDTH-1) loop
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s_master_local_adress <= std_logic_vector(to_unsigned(i, C_ADDRESS_WIDTH));
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s_master_local_ren <= '1';
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wait until rising_edge(s_wb_clk);
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s_master_local_adress <= (others => '0');
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s_master_local_ren <= '0';
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wait until rising_edge(s_wb_clk) and s_master_local_ack = '1';
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sv_wishbone_queue.pop(v_wbmaster_data);
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assert_equal(s_master_local_dout, v_wbmaster_data);
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end loop;
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report "INFO: Test successfully finished!";
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s_test_done <= true;
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wait;
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end process WbMasterLocalP;
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i_WishBoneMasterE : WishBoneMasterE
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generic map (
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G_ADR_WIDTH => C_ADDRESS_WIDTH,
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G_DATA_WIDTH => C_DATA_WIDTH
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)
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port map (
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--+ wishbone system if
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WbRst_i => s_wb_reset,
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WbClk_i => s_wb_clk,
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--+ wishbone outputs
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WbCyc_o => s_wb_cyc,
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WbStb_o => s_wb_stb,
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WbWe_o => s_wb_we,
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WbAdr_o => s_wb_adr,
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WbDat_o => s_wb_master_data,
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--+ wishbone inputs
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WbDat_i => s_wb_slave_data,
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WbAck_i => s_wb_ack,
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WbErr_i => s_wb_err,
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--+ local register if
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LocalWen_i => s_master_local_wen,
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LocalRen_i => s_master_local_ren,
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LocalAdress_i => s_master_local_adress,
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LocalData_i => s_master_local_din,
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LocalData_o => s_master_local_dout,
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LocalAck_o => s_master_local_ack,
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LocalError_o => s_master_local_error
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);
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i_WishBoneSlaveE : WishBoneSlaveE
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generic map (
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G_ADR_WIDTH => C_ADDRESS_WIDTH,
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G_DATA_WIDTH => C_DATA_WIDTH
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)
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port map (
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--+ wishbone system if
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WbRst_i => s_wb_reset,
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WbClk_i => s_wb_clk,
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--+ wishbone inputs
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WbCyc_i => s_wb_cyc,
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WbStb_i => s_wb_stb,
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WbWe_i => s_wb_we,
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WbAdr_i => s_wb_adr,
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WbDat_i => s_wb_master_data,
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--* wishbone outputs
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WbDat_o => s_wb_slave_data,
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WbAck_o => s_wb_ack,
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WbErr_o => s_wb_err,
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--+ local register if
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LocalWen_o => s_slave_local_wen,
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LocalRen_o => s_slave_local_ren,
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LocalAdress_o => s_slave_local_adress,
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LocalData_o => s_slave_local_dout,
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LocalData_i => s_slave_local_din
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);
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WbSlaveLocalP : process (s_wb_clk) is
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variable v_register : t_register := (others => (others => '0'));
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begin
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if (rising_edge(s_wb_clk)) then
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if (s_wb_reset = '1') then
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v_register := (others => (others => '0'));
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s_slave_local_din <= (others => '0');
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else
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if (s_slave_local_wen = '1') then
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v_register(to_integer(unsigned(s_slave_local_adress))) := s_slave_local_dout;
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elsif (s_slave_local_ren = '1') then
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s_slave_local_din <= v_register(to_integer(unsigned(s_slave_local_adress)));
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end if;
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end if;
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end if;
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end process WbSlaveLocalP;
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end architecture sim;
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