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147 lines
4.3 KiB
147 lines
4.3 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--+ including vhdl 2008 libraries
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--+ These lines can be commented out when using
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--+ a simulator with built-in VHDL 2008 support
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--library ieee_proposed;
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-- use ieee_proposed.standard_additions.all;
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-- use ieee_proposed.std_logic_1164_additions.all;
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-- use ieee_proposed.numeric_std_additions.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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library libvhdl;
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use libvhdl.AssertP.all;
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use libvhdl.SimP.all;
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use libvhdl.QueueP.all;
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use libvhdl.UtilsP.all;
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entity SimT is
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end entity SimT;
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architecture sim of SimT is
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--* testbench global clock period
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constant C_PERIOD : time := 5 ns;
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--* SPI data transfer data width
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constant C_DATA_WIDTH : natural := 8;
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signal s_tests_done : boolean_vector(0 to 1) := (others => false);
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signal s_clk : std_logic := '0';
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signal s_sclk : std_logic;
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signal s_ste : std_logic;
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signal s_mosi : std_logic;
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signal s_miso : std_logic;
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shared variable sv_mosi_queue : t_list_queue;
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shared variable sv_miso_queue : t_list_queue;
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begin
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s_clk <= not(s_clk) after C_PERIOD when not(and_reduce(s_tests_done)) else '0';
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QueueInitP : process is
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begin
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sv_mosi_queue.init(32);
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sv_miso_queue.init(32);
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wait;
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end process QueueInitP;
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SimTestP : process is
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variable v_time : time;
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begin
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wait until s_clk = '1';
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v_time := now;
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wait_cycles(s_clk, 10);
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assert (now - v_time) = C_PERIOD * 20
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severity failure;
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s_tests_done(0) <= true;
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report "INFO: wait_cycles() procedure tests finished successfully";
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wait;
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end process SimTestP;
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-- Unit test of spi master procedure, checks all combinations
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-- of cpol & cpha against spi slave procedure
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SpiMasterP : process is
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variable v_send_data : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
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variable v_receive_data : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
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variable v_queue_data : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
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variable v_random : RandomPType;
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begin
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v_random.InitSeed(v_random'instance_name);
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for direction in 0 to 1 loop
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for mode in 0 to 3 loop
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for i in 0 to 255 loop
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v_send_data := v_random.RandSlv(C_DATA_WIDTH);
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sv_mosi_queue.push(v_send_data);
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spi_master (data_in => v_send_data,
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data_out => v_receive_data,
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sclk => s_sclk,
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ste => s_ste,
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mosi => s_mosi,
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miso => s_miso,
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dir => direction,
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cpol => mode / 2,
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cpha => mode mod 2,
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period => 1 us
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);
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sv_miso_queue.pop(v_queue_data);
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assert_equal(v_receive_data, v_queue_data);
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end loop;
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end loop;
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end loop;
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wait;
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end process SpiMasterP;
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-- Unit test of spi slave procedure, checks all combinations
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-- of cpol & cpha against spi master procedure
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SpiSlaveP : process is
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variable v_send_data : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
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variable v_receive_data : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
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variable v_queue_data : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
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variable v_random : RandomPType;
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begin
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v_random.InitSeed(v_random'instance_name);
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for direction in 0 to 1 loop
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for mode in 0 to 3 loop
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for i in 0 to 255 loop
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v_send_data := v_random.RandSlv(C_DATA_WIDTH);
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sv_miso_queue.push(v_send_data);
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spi_slave (data_in => v_send_data,
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data_out => v_receive_data,
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sclk => s_sclk,
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ste => s_ste,
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mosi => s_mosi,
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miso => s_miso,
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dir => direction,
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cpol => mode / 2,
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cpha => mode mod 2
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);
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sv_mosi_queue.pop(v_queue_data);
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assert_equal(v_receive_data, v_queue_data);
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end loop;
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end loop;
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end loop;
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report "INFO: All tests of valid spi_master() & spi_slave() combinations finished successfully";
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s_tests_done(1) <= true;
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wait;
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end process SpiSlaveP;
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end architecture sim;
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