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Library of reusable VHDL components
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libvhdl/syn
T. Meissner 7d60f0ae1b add simple wishbone master and slave with support of classic single write and read as specified in the wishbone spec b4; add unit tests for wishbone m,aster & slave 11 years ago
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SpiMasterE.vhd add generic G_DATA_DIR to set if we want transfer from LSB to MSB ore vice versa 11 years ago
SpiSlaveE.vhd add generic G_DATA_DIR to set if we want transfer from LSB to MSB ore vice versa 11 years ago
WishBoneMasterE.vhd add simple wishbone master and slave with support of classic single write and read as specified in the wishbone spec b4; add unit tests for wishbone m,aster & slave 11 years ago
WishBoneSlaveE.vhd add simple wishbone master and slave with support of classic single write and read as specified in the wishbone spec b4; add unit tests for wishbone m,aster & slave 11 years ago