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242 lines
7.2 KiB
242 lines
7.2 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity WishBoneMasterE is
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generic (
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Coverage : boolean := false;
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Formal : boolean := false;
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Simulation : boolean := false;
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AddressWidth : natural := 8;
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DataWidth : natural := 8
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);
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port (
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--+ wishbone system if
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WbRst_i : in std_logic;
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WbClk_i : in std_logic;
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--+ wishbone outputs
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WbCyc_o : out std_logic;
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WbStb_o : out std_logic;
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WbWe_o : out std_logic;
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WbAdr_o : out std_logic_vector(AddressWidth-1 downto 0);
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WbDat_o : out std_logic_vector(DataWidth-1 downto 0);
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--+ wishbone inputs
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WbDat_i : in std_logic_vector(DataWidth-1 downto 0);
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WbAck_i : in std_logic;
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WbErr_i : in std_logic;
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--+ local register if
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LocalWen_i : in std_logic;
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LocalRen_i : in std_logic;
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LocalAdress_i : in std_logic_vector(AddressWidth-1 downto 0);
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LocalData_i : in std_logic_vector(DataWidth-1 downto 0);
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LocalData_o : out std_logic_vector(DataWidth-1 downto 0);
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LocalAck_o : out std_logic;
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LocalError_o : out std_logic
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);
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end entity WishBoneMasterE;
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architecture rtl of WishBoneMasterE is
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type t_wb_master_fsm is (IDLE, ADDRESS, DATA);
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signal s_wb_master_fsm : t_wb_master_fsm;
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signal s_wb_wen : std_logic;
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begin
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--+ Wishbone master control state machine
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WbMasterStatesP : process (WbClk_i) is
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begin
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if (rising_edge(WbClk_i)) then
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if (WbRst_i = '1') then
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s_wb_master_fsm <= IDLE;
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else
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WbReadC : case s_wb_master_fsm is
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when IDLE =>
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if ((LocalWen_i xor LocalRen_i) = '1') then
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s_wb_master_fsm <= ADDRESS;
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end if;
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when ADDRESS =>
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if (WbAck_i = '1' or WbErr_i = '1') then
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s_wb_master_fsm <= IDLE;
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else
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s_wb_master_fsm <= DATA;
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end if;
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when DATA =>
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if (WbErr_i = '1' or WbAck_i = '1') then
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s_wb_master_fsm <= IDLE;
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end if;
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when others =>
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s_wb_master_fsm <= IDLE;
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end case;
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end if;
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end if;
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end process WbMasterStatesP;
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--+ combinatoral local register if outputs
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LocalData_o <= WbDat_i when s_wb_master_fsm = DATA else (others => '0');
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LocalError_o <= WbErr_i when s_wb_master_fsm /= IDLE else '0';
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LocalAck_o <= WbAck_i when (s_wb_master_fsm = ADDRESS or s_wb_master_fsm = DATA) and WbErr_i = '0' else '0';
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--+ combinatoral wishbone if outputs
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WbStb_o <= '1' when s_wb_master_fsm /= IDLE else '0';
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WbCyc_o <= '1' when s_wb_master_fsm /= IDLE else '0';
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WbWe_o <= s_wb_wen when s_wb_master_fsm /= IDLE else '0';
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--+ registered wishbone if outputs
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OutRegsP : process (WbClk_i) is
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begin
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if (rising_edge(WbClk_i)) then
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if (WbRst_i = '1') then
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WbAdr_o <= (others => '0');
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WbDat_o <= (others => '0');
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s_wb_wen <= '0';
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else
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if (s_wb_master_fsm = IDLE) then
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if ((LocalWen_i xor LocalRen_i) = '1') then
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WbAdr_o <= LocalAdress_i;
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s_wb_wen <= LocalWen_i;
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end if;
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if (LocalWen_i = '1') then
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WbDat_o <= LocalData_i;
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end if;
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end if;
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end if;
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end if;
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end process OutRegsP;
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default clock is rising_edge(WbClk_i);
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FormalG : if Formal generate
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-- Glue logic
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signal s_local_data : std_logic_vector(DataWidth-1 downto 0);
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signal s_local_address : std_logic_vector(AddressWidth-1 downto 0);
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begin
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process is
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begin
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wait until rising_edge(WbClk_i);
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if (s_wb_master_fsm = IDLE) then
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if (LocalWen_i = '1') then
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s_local_data <= LocalData_i;
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s_local_address <= LocalAdress_i;
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end if;
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if (LocalRen_i = '1') then
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s_local_address <= LocalAdress_i;
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end if;
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end if;
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end process;
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restrict {WbRst_i = '1'; WbRst_i = '0'[+]}[*1];
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RESET : assert always
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WbRst_i -> next
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WbCyc_o = '0' and WbStb_o = '0' and WbWe_o = '0' and
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to_integer(unsigned(WbAdr_o)) = 0 and to_integer(unsigned(WbDat_o)) = 0 and
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LocalAck_o = '0' and LocalError_o = '0' and to_integer(unsigned(LocalData_o)) = 0
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report "WB master: Reset error";
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WB_WRITE : assert always
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((not WbCyc_o and not WbStb_o and LocalWen_i and not LocalRen_i) ->
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next (WbCyc_o and WbStb_o and WbWe_o)) abort WbRst_i
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report "WB master: Write error";
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WB_READ : assert always
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((not WbCyc_o and not WbStb_o and LocalRen_i and not LocalWen_i) ->
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next (WbCyc_o and WbStb_o and not WbWe_o)) abort WbRst_i
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report "WB master: Read error";
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assert never LocalError_o and LocalAck_o;
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assert always WbStb_o = WbCyc_o;
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assert always
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not WbRst_i and WbCyc_o and not WbAck_i and not WbErr_i ->
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next (WbCyc_o until (WbAck_i or WbErr_i)) abort WbRst_i;
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assert always WbCyc_o and WbAck_i -> next not WbCyc_o;
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assert always WbWe_o and WbAck_i -> next not WbWe_o;
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assert always WbWe_o -> WbCyc_o;
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assert always WbWe_o -> WbDat_o = s_local_data abort WbRst_i;
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assert always WbWe_o -> WbAdr_o = s_local_address abort WbRst_i;
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assert always WbCyc_o and not WbWe_o -> WbAdr_o = s_local_address abort WbRst_i;
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end generate FormalG;
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CoverageG : if Coverage generate
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restrict {WbRst_i = '1'; WbRst_i = '0'[+]}[*1];
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COVER_LOCAL_WRITE : cover {s_wb_master_fsm = IDLE and LocalWen_i = '1' and
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LocalRen_i = '0' and WbRst_i = '0'}
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report "WB master: Local write";
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COVER_LOCAL_READ : cover {s_wb_master_fsm = IDLE and LocalRen_i = '1' and
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LocalWen_i = '0' and WbRst_i = '0'}
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report "WB master: Local read";
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COVER_LOCAL_WRITE_READ : cover {s_wb_master_fsm = IDLE and LocalWen_i = '1' and
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LocalRen_i = '1' and WbRst_i = '0'}
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report "WB master: Local write & read";
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end generate CoverageG;
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SimulationG : if Simulation generate
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-- assert directives
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RESET : assert always
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WbRst_i ->
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WbCyc_o = '0' and WbStb_o = '0' and WbWe_o = '0' and
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to_integer(unsigned(WbAdr_o)) = 0 and to_integer(unsigned(WbDat_o)) = 0 and
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LocalAck_o = '0' and LocalError_o = '0' and to_integer(unsigned(LocalData_o)) = 0
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report "WB master: Reset error";
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WB_WRITE : assert always
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((not(WbCyc_o) and not(WbStb_o) and LocalWen_i and not (LocalRen_i)) ->
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next (WbCyc_o = '1' and WbStb_o = '1' and WbWe_o = '1')) abort WbRst_i
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report "WB master: Write error";
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WB_READ : assert always
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((not(WbCyc_o) and not(WbStb_o) and LocalRen_i and not(LocalWen_i)) ->
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next (WbCyc_o = '1' and WbStb_o = '1' and WbWe_o = '0')) abort WbRst_i
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report "WB master: Read error";
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-- cover directives
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COVER_LOCAL_WRITE : cover {s_wb_master_fsm = IDLE and LocalWen_i = '1' and
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LocalRen_i = '0' and WbRst_i = '0'}
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report "WB master: Local write";
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COVER_LOCAL_READ : cover {s_wb_master_fsm = IDLE and LocalRen_i = '1' and
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LocalWen_i = '0' and WbRst_i = '0'}
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report "WB master: Local read";
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COVER_LOCAL_WRITE_READ : cover {s_wb_master_fsm = IDLE and LocalWen_i = '1' and
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LocalRen_i = '1' and WbRst_i = '0'}
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report "WB master: Local write & read";
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end generate SimulationG;
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end architecture rtl;
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