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353 lines
10 KiB
353 lines
10 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--+ including vhdl 2008 libraries
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--+ These lines can be commented out when using
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--+ a simulator with built-in VHDL 2008 support
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library ieee_proposed;
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use ieee_proposed.standard_additions.all;
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use ieee_proposed.std_logic_1164_additions.all;
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use ieee_proposed.numeric_std_additions.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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library libvhdl;
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use libvhdl.AssertP.all;
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use libvhdl.SimP.all;
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use libvhdl.QueueP.all;
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entity SpiT is
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end entity SpiT;
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architecture sim of SpiT is
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component SpiMasterE is
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generic (
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G_DATA_WIDTH : positive := 8;
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G_SPI_CPOL : natural range 0 to 1 := 0;
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G_SPI_CPHA : natural range 0 to 1 := 0;
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G_SCLK_DIVIDER : positive range 6 to positive'high := 10
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);
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port (
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--+ system if
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Reset_n_i : in std_logic;
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Clk_i : in std_logic;
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--+ SPI slave if
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SpiSclk_o : out std_logic;
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SpiSte_o : out std_logic;
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SpiMosi_o : out std_logic;
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SpiMiso_i : in std_logic;
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--+ local VAI if
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Data_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
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DataValid_i : in std_logic;
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DataAccept_o : out std_logic;
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Data_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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DataValid_o : out std_logic;
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DataAccept_i : in std_logic
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);
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end component SpiMasterE;
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component SpiSlaveE is
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generic (
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G_DATA_WIDTH : positive := 8;
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G_SPI_CPOL : natural range 0 to 1 := 0;
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G_SPI_CPHA : natural range 0 to 1 := 0
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);
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port (
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--+ system if
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Reset_n_i : in std_logic;
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Clk_i : in std_logic;
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--+ SPI slave if
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SpiSclk_i : in std_logic;
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SpiSte_i : in std_logic;
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SpiMosi_i : in std_logic;
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SpiMiso_o : out std_logic;
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--+ local VAI if
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Data_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
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DataValid_i : in std_logic;
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DataAccept_o : out std_logic;
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Data_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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DataValid_o : out std_logic;
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DataAccept_i : in std_logic
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);
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end component SpiSlaveE;
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--* testbench global clock period
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constant C_PERIOD : time := 5 ns;
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--* SPI data transfer data width
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constant C_DATA_WIDTH : natural := 8;
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--* testbench global clock
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signal s_clk : std_logic := '0';
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--* testbench global reset
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signal s_reset_n : std_logic := '0';
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--* SPI mode range subtype
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subtype t_spi_mode is natural range 0 to 3;
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--+ test done array with entry for each test
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signal s_test_done : boolean_vector(t_spi_mode'low to 2*t_spi_mode'high+1) := (others => false);
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begin
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--* testbench global clock
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s_clk <= not(s_clk) after C_PERIOD/2 when not(and_reduce(s_test_done)) else '0';
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--* testbench global reset
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s_reset_n <= '1' after 100 ns;
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--+ SpiMasterE tests for all 4 modes
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SpiMastersG : for mode in t_spi_mode'low to t_spi_mode'high generate
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signal s_sclk : std_logic;
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signal s_ste : std_logic;
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signal s_mosi : std_logic;
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signal s_miso : std_logic;
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signal s_din : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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signal s_din_valid : std_logic;
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signal s_din_accept : std_logic;
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signal s_dout : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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signal s_dout_valid : std_logic;
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signal s_dout_accept : std_logic;
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shared variable sv_mosi_queue : t_list_queue;
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shared variable sv_miso_queue : t_list_queue;
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begin
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SpiMasterStimP : process is
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variable v_random : RandomPType;
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begin
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v_random.InitSeed(v_random'instance_name);
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s_din_valid <= '0';
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s_din <= (others => '0');
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wait until s_reset_n = '1';
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for i in 0 to integer'(2**C_DATA_WIDTH-1) loop
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s_din <= v_random.RandSlv(C_DATA_WIDTH);
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s_din_valid <= '1';
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wait until rising_edge(s_clk) and s_din_accept = '1';
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s_din_valid <= '0';
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sv_mosi_queue.push(s_din);
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wait until rising_edge(s_clk);
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end loop;
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wait;
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end process SpiMasterStimP;
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i_SpiMasterE : SpiMasterE
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generic map (
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G_DATA_WIDTH => C_DATA_WIDTH,
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G_SPI_CPOL => mode / 2,
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G_SPI_CPHA => mode mod 2,
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G_SCLK_DIVIDER => 10
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)
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port map (
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--+ system if
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Reset_n_i => s_reset_n,
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Clk_i => s_clk,
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--+ SPI slave if
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SpiSclk_o => s_sclk,
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SpiSte_o => s_ste,
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SpiMosi_o => s_mosi,
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SpiMiso_i => s_miso,
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--+ local VAI if
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Data_i => s_din,
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DataValid_i => s_din_valid,
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DataAccept_o => s_din_accept,
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Data_o => s_dout,
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DataValid_o => s_dout_valid,
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DataAccept_i => s_dout_accept
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);
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SpiMasterCheckP : process is
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variable v_queue_data : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
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begin
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s_dout_accept <= '0';
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wait until s_reset_n = '1';
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for i in 0 to integer'(2**C_DATA_WIDTH-1) loop
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wait until rising_edge(s_clk) and s_dout_valid = '1';
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s_dout_accept <= '1';
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sv_miso_queue.pop(v_queue_data);
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assert_equal(s_dout, v_queue_data);
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wait until rising_edge(s_clk);
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s_dout_accept <= '0';
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end loop;
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report "INFO: SpiMaster (mode=" & to_string(mode) & ") test successfully";
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s_test_done(mode) <= true;
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wait;
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end process SpiMasterCheckP;
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-- Unit test of spi slave procedure, checks all combinations
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-- of cpol & cpha against spi master procedure
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SpiSlaveP : process is
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variable v_send_data : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
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variable v_receive_data : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
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variable v_queue_data : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
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variable v_random : RandomPType;
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begin
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v_random.InitSeed(v_random'instance_name);
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wait until s_reset_n = '1';
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for i in 0 to integer'(2**C_DATA_WIDTH-1) loop
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v_send_data := v_random.RandSlv(C_DATA_WIDTH);
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sv_miso_queue.push(v_send_data);
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spi_slave (data_in => v_send_data,
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data_out => v_receive_data,
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sclk => s_sclk,
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ste => s_ste,
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mosi => s_mosi,
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miso => s_miso,
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cpol => mode / 2,
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cpha => mode mod 2
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);
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sv_mosi_queue.pop(v_queue_data);
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assert_equal(v_receive_data, v_queue_data);
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end loop;
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wait;
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end process SpiSlaveP;
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end generate SpiMastersG;
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--+ SpiSlaveE tests for all 4 modes
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SpiSlavesG : for mode in t_spi_mode'low to t_spi_mode'high generate
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signal s_sclk : std_logic;
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signal s_ste : std_logic;
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signal s_mosi : std_logic;
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signal s_miso : std_logic;
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signal s_din : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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signal s_din_valid : std_logic;
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signal s_din_accept : std_logic;
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signal s_dout : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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signal s_dout_valid : std_logic;
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signal s_dout_accept : std_logic;
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shared variable sv_mosi_queue : t_list_queue;
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shared variable sv_miso_queue : t_list_queue;
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begin
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--* Unit test of spi master procedure, checks all combinations
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--* of cpol & cpha against spi slave procedure
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SpiMasterP : process is
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variable v_send_data : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
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variable v_receive_data : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
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variable v_queue_data : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
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variable v_random : RandomPType;
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begin
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v_random.InitSeed(v_random'instance_name);
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s_sclk <= '1';
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s_ste <= '1';
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s_mosi <= '1';
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wait until s_reset_n = '1';
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for i in 0 to integer'(2**C_DATA_WIDTH-1) loop
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v_send_data := v_random.RandSlv(C_DATA_WIDTH);
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sv_mosi_queue.push(v_send_data);
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spi_master (data_in => v_send_data,
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data_out => v_receive_data,
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sclk => s_sclk,
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ste => s_ste,
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mosi => s_mosi,
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miso => s_miso,
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cpol => mode / 2,
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cpha => mode mod 2,
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period => 100 ns
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);
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sv_miso_queue.pop(v_queue_data);
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assert_equal(v_receive_data, v_queue_data);
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end loop;
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report "INFO: SpiSlave (mode=" & to_string(mode) & ") test successfully";
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s_test_done(mode+4) <= true;
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wait;
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end process SpiMasterP;
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SpiSlaveStimP : process is
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variable v_random : RandomPType;
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begin
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v_random.InitSeed(v_random'instance_name);
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s_din_valid <= '0';
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s_din <= (others => '0');
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wait until s_reset_n = '1';
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for i in 0 to integer'(2**C_DATA_WIDTH-1) loop
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s_din <= v_random.RandSlv(C_DATA_WIDTH);
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s_din_valid <= '1';
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wait until rising_edge(s_clk) and s_din_accept = '1';
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s_din_valid <= '0';
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sv_miso_queue.push(s_din);
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wait until rising_edge(s_clk) and s_dout_valid = '1';
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end loop;
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wait;
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end process SpiSlaveStimP;
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i_SpiSlaveE : SpiSlaveE
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generic map (
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G_DATA_WIDTH => C_DATA_WIDTH,
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G_SPI_CPOL => mode / 2,
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G_SPI_CPHA => mode mod 2
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)
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port map (
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--+ system if
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Reset_n_i => s_reset_n,
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Clk_i => s_clk,
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--+ SPI slave if
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SpiSclk_i => s_sclk,
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SpiSte_i => s_ste,
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SpiMosi_i => s_mosi,
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SpiMiso_o => s_miso,
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--+ local VAI if
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Data_i => s_din,
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DataValid_i => s_din_valid,
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DataAccept_o => s_din_accept,
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Data_o => s_dout,
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DataValid_o => s_dout_valid,
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DataAccept_i => s_dout_accept
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);
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SpiSlaveCheckP : process is
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variable v_queue_data : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
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begin
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s_dout_accept <= '0';
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wait until s_reset_n = '1';
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for i in 0 to integer'(2**C_DATA_WIDTH-1) loop
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wait until rising_edge(s_clk) and s_dout_valid = '1';
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s_dout_accept <= '1';
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sv_mosi_queue.pop(v_queue_data);
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assert_equal(s_dout, v_queue_data);
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wait until rising_edge(s_clk);
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s_dout_accept <= '0';
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end loop;
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wait;
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end process SpiSlaveCheckP;
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end generate SpiSlavesG;
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end architecture sim;
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