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90 lines
2.6 KiB
90 lines
2.6 KiB
library ieee;
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use ieee.std_logic_1164.all;
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entity WishBoneSlaveE is
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generic (
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G_ADR_WIDTH : positive := 8; --* address bus width
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G_DATA_WIDTH : positive := 8 --* data bus width
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);
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port (
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--+ wishbone system if
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WbRst_i : in std_logic;
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WbClk_i : in std_logic;
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--+ wishbone inputs
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WbCyc_i : in std_logic;
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WbStb_i : in std_logic;
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WbWe_i : in std_logic;
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WbAdr_i : in std_logic_vector(G_ADR_WIDTH-1 downto 0);
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WbDat_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
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--+ wishbone outputs
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WbDat_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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WbAck_o : out std_logic;
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WbErr_o : out std_logic;
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--+ local register if
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LocalWen_o : out std_logic;
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LocalRen_o : out std_logic;
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LocalAdress_o : out std_logic_vector(G_ADR_WIDTH-1 downto 0);
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LocalData_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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LocalData_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0)
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);
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end entity WishBoneSlaveE;
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architecture rtl of WishBoneSlaveE is
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type t_wb_slave_fsm is (IDLE, ADDRESS, DATA);
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signal s_wb_slave_fsm : t_wb_slave_fsm;
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signal s_wb_active : boolean;
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begin
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WbSlaveControlP : process (WbClk_i) is
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begin
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if (rising_edge(WbClk_i)) then
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if (WbRst_i = '1') then
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s_wb_slave_fsm <= IDLE;
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else
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WbReadC : case s_wb_slave_fsm is
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when IDLE =>
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s_wb_slave_fsm <= ADDRESS;
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when ADDRESS =>
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if (s_wb_active and WbWe_i = '0') then
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s_wb_slave_fsm <= DATA;
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end if;
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when DATA =>
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s_wb_slave_fsm <= ADDRESS;
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when others =>
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s_wb_slave_fsm <= IDLE;
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end case;
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end if;
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end if;
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end process WbSlaveControlP;
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s_wb_active <= true when s_wb_slave_fsm /= IDLE and WbCyc_i = '1' and WbStb_i = '1' else false;
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--+ local register if outputs
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LocalWen_o <= WbWe_i when s_wb_slave_fsm = ADDRESS and s_wb_active else '0';
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LocalRen_o <= not(WbWe_i) when s_wb_slave_fsm = ADDRESS and s_wb_active else '0';
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LocalAdress_o <= WbAdr_i when s_wb_slave_fsm /= IDLE and s_wb_active else (others => '0');
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LocalData_o <= WbDat_i when s_wb_slave_fsm = ADDRESS and s_wb_active and WbWe_i = '1' else (others => '0');
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--+ wishbone if outputs
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WbDat_o <= LocalData_i when s_wb_slave_fsm = DATA and WbWe_i = '0' else (others => '0');
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WbAck_o <= '1' when s_wb_slave_fsm = DATA or (s_wb_slave_fsm = ADDRESS and s_wb_active and WbWe_i = '1') else '0';
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WbErr_o <= '0';
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end architecture rtl;
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