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99 lines
2.4 KiB
99 lines
2.4 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library libvhdl;
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use libvhdl.StringP.all;
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use libvhdl.AssertP.all;
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use libvhdl.SimP.all;
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entity SimT is
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end entity SimT;
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architecture sim of SimT is
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constant C_PERIOD : time := 5 ns;
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signal s_done : boolean := false;
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signal s_clk : std_logic := '0';
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signal s_sclk : std_logic;
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signal s_ste : std_logic;
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signal s_mosi : std_logic;
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signal s_miso : std_logic;
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begin
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s_clk <= not(s_clk) after C_PERIOD when not(s_done) else '0';
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SimTestP : process is
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variable v_time : time;
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begin
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wait until s_clk = '1';
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v_time := now;
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wait_cycles(s_clk, 10);
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assert (now - v_time) = C_PERIOD * 20
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severity failure;
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s_done <= true;
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wait;
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end process SimTestP;
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-- Unit test of spi master procedure, checks all combinations
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-- of cpol & cpha against spi slave procedure
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SpiMasterP : process is
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variable v_slave_data : std_logic_vector(7 downto 0);
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begin
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for mode in 0 to 3 loop
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for i in 0 to 255 loop
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spi_master (data_in => std_logic_vector(to_unsigned(i, 8)),
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data_out => v_slave_data,
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sclk => s_sclk,
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ste => s_ste,
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mosi => s_mosi,
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miso => s_miso,
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cpol => mode / 2,
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cpha => mode mod 2,
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period => 1 us
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);
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assert_equal(v_slave_data, std_logic_vector(to_unsigned(i, 8)));
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end loop;
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end loop;
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wait;
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end process SpiMasterP;
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-- Unit test of spi slave procedure, checks all combinations
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-- of cpol & cpha against spi master procedure
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SpiSlaveP : process is
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variable v_master_data : std_logic_vector(7 downto 0);
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begin
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for mode in 0 to 3 loop
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for i in 0 to 255 loop
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spi_slave (data_in => std_logic_vector(to_unsigned(i, 8)),
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data_out => v_master_data,
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sclk => s_sclk,
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ste => s_ste,
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mosi => s_mosi,
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miso => s_miso,
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cpol => mode / 2,
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cpha => mode mod 2
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);
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assert_equal(v_master_data, std_logic_vector(to_unsigned(i, 8)));
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end loop;
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end loop;
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wait;
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report "INFO: SimP tests finished successfully";
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end process SpiSlaveP;
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end architecture sim;
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