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328 lines
11 KiB
328 lines
11 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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use osvvm.CoveragePkg.all;
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library libvhdl;
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use libvhdl.AssertP.all;
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use libvhdl.SimP.all;
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use libvhdl.UtilsP.all;
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library std;
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use std.env.all;
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entity WishBoneT is
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end entity WishBoneT;
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architecture sim of WishBoneT is
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component WishBoneMasterE is
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generic (
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G_ADR_WIDTH : positive := 8; --* address bus width
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G_DATA_WIDTH : positive := 8 --* data bus width
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);
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port (
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--+ wishbone system if
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WbRst_i : in std_logic;
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WbClk_i : in std_logic;
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--+ wishbone outputs
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WbCyc_o : out std_logic;
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WbStb_o : out std_logic;
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WbWe_o : out std_logic;
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WbAdr_o : out std_logic_vector(G_ADR_WIDTH-1 downto 0);
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WbDat_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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--+ wishbone inputs
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WbDat_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
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WbAck_i : in std_logic;
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WbErr_i : in std_logic;
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--+ local register if
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LocalWen_i : in std_logic;
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LocalRen_i : in std_logic;
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LocalAdress_i : in std_logic_vector(G_ADR_WIDTH-1 downto 0);
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LocalData_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
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LocalData_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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LocalAck_o : out std_logic;
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LocalError_o : out std_logic
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);
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end component WishBoneMasterE;
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component WishBoneSlaveE is
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generic (
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G_ADR_WIDTH : positive := 8; --* address bus width
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G_DATA_WIDTH : positive := 8 --* data bus width
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);
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port (
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--+ wishbone system if
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WbRst_i : in std_logic;
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WbClk_i : in std_logic;
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--+ wishbone inputs
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WbCyc_i : in std_logic;
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WbStb_i : in std_logic;
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WbWe_i : in std_logic;
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WbAdr_i : in std_logic_vector(G_ADR_WIDTH-1 downto 0);
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WbDat_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
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--* wishbone outputs
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WbDat_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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WbAck_o : out std_logic;
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WbErr_o : out std_logic;
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--+ local register if
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LocalWen_o : out std_logic;
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LocalRen_o : out std_logic;
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LocalAdress_o : out std_logic_vector(G_ADR_WIDTH-1 downto 0);
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LocalData_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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LocalData_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0)
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);
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end component WishBoneSlaveE;
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--* testbench global clock period
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constant C_PERIOD : time := 5 ns;
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--* Wishbone data width
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constant C_DATA_WIDTH : natural := 8;
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--* Wishbone address width
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constant C_ADDRESS_WIDTH : natural := 8;
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type t_wishbone is record
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--+ wishbone outputs
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Cyc : std_logic;
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Stb : std_logic;
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We : std_logic;
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Adr : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0);
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WDat : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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--+ wishbone inputs
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RDat : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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Ack : std_logic;
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Err : std_logic;
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end record t_wishbone;
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signal s_wishbone : t_wishbone := ('Z', 'Z', 'Z', (others => 'Z'), (others => 'Z'), (others => 'Z'), 'Z', 'Z');
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--* testbench global clock
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signal s_wb_clk : std_logic := '1';
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--* testbench global reset
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signal s_wb_reset : std_logic := '1';
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signal s_master_local_wen : std_logic;
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signal s_master_local_ren : std_logic;
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signal s_master_local_adress : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0);
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signal s_master_local_din : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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signal s_master_local_dout : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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signal s_master_local_ack : std_logic;
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signal s_master_local_error : std_logic;
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signal s_slave_local_wen : std_logic;
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signal s_slave_local_ren : std_logic;
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signal s_slave_local_adress : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0);
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signal s_slave_local_dout : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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signal s_slave_local_din : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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type t_register is array (0 to integer'(2**C_ADDRESS_WIDTH-1)) of std_logic_vector(C_DATA_WIDTH-1 downto 0);
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package SlvQueue is new libvhdl.QueueP
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generic map (
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QUEUE_TYPE => std_logic_vector(C_ADDRESS_WIDTH-1 downto 0),
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MAX_LEN => 2**C_ADDRESS_WIDTH,
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to_string => to_hstring
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);
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shared variable sv_wishbone_queue : SlvQueue.t_list_queue;
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package IntSlvDict is new libvhdl.DictP
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generic map (KEY_TYPE => integer,
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VALUE_TYPE => std_logic_vector,
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key_to_string => to_string,
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value_to_string => to_hstring);
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shared variable sv_wishbone_dict : IntSlvDict.t_dict;
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shared variable sv_coverage : CovPType;
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begin
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--* testbench global clock
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s_wb_clk <= not(s_wb_clk) after C_PERIOD/2;
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--* testbench global reset
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s_wb_reset <= '0' after C_PERIOD * 5;
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QueueInitP : process is
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begin
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sv_wishbone_queue.init(false);
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sv_wishbone_dict.init(false);
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wait;
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end process QueueInitP;
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WbMasterLocalP : process is
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variable v_random : RandomPType;
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variable v_wbmaster_address : integer;
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variable v_master_local_adress : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0);
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variable v_wbmaster_data : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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begin
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v_random.InitSeed(v_random'instance_name);
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v_wbmaster_data := (others => '0');
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s_master_local_din <= (others => '0');
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s_master_local_adress <= (others => '0');
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s_master_local_wen <= '0';
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s_master_local_ren <= '0';
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wait until s_wb_reset = '0';
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-- write the wishbone slave registers
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sv_coverage.AddBins(GenBin(0));
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sv_coverage.AddBins(GenBin(integer'(2**C_ADDRESS_WIDTH-1)));
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sv_coverage.AddBins(GenBin(1, integer'(2**C_ADDRESS_WIDTH-2), 64));
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while not sv_coverage.IsCovered loop
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v_wbmaster_address := sv_coverage.RandCovPoint;
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v_wbmaster_data := v_random.RandSlv(C_DATA_WIDTH);
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s_master_local_din <= v_wbmaster_data;
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s_master_local_adress <= uint_to_slv(v_wbmaster_address, C_ADDRESS_WIDTH);
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s_master_local_wen <= '1';
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wait until rising_edge(s_wb_clk);
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s_master_local_din <= (others => '0');
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s_master_local_adress <= (others => '0');
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s_master_local_wen <= '0';
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wait until rising_edge(s_wb_clk) and s_master_local_ack = '1';
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sv_wishbone_queue.push(uint_to_slv(v_wbmaster_address, C_ADDRESS_WIDTH));
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sv_wishbone_dict.set(v_wbmaster_address, v_wbmaster_data);
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sv_coverage.ICover(v_wbmaster_address);
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end loop;
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-- read back and check the wishbone slave registers
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while not(sv_wishbone_queue.is_empty) loop
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sv_wishbone_queue.pop(v_master_local_adress);
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s_master_local_adress <= v_master_local_adress;
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s_master_local_ren <= '1';
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wait until rising_edge(s_wb_clk);
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s_master_local_adress <= (others => '0');
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s_master_local_ren <= '0';
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wait until rising_edge(s_wb_clk) and s_master_local_ack = '1';
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sv_wishbone_dict.get(slv_to_uint(v_master_local_adress), v_wbmaster_data);
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assert_equal(s_master_local_dout, v_wbmaster_data);
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end loop;
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-- test local write & read at the same time
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wait until rising_edge(s_wb_clk);
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s_master_local_wen <= '1';
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s_master_local_ren <= '1';
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wait until rising_edge(s_wb_clk);
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s_master_local_wen <= '0';
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s_master_local_ren <= '0';
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wait until rising_edge(s_wb_clk);
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-- Test finished
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report "INFO: Test successfully finished!";
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sv_coverage.SetMessage("WishboneT coverage results");
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sv_coverage.WriteBin;
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finish;
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wait;
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end process WbMasterLocalP;
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i_WishBoneMasterE : WishBoneMasterE
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generic map (
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G_ADR_WIDTH => C_ADDRESS_WIDTH,
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G_DATA_WIDTH => C_DATA_WIDTH
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)
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port map (
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--+ wishbone system if
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WbRst_i => s_wb_reset,
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WbClk_i => s_wb_clk,
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--+ wishbone outputs
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WbCyc_o => s_wishbone.Cyc,
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WbStb_o => s_wishbone.Stb,
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WbWe_o => s_wishbone.We,
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WbAdr_o => s_wishbone.Adr,
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WbDat_o => s_wishbone.WDat,
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--+ wishbone inputs
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WbDat_i => s_wishbone.RDat,
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WbAck_i => s_wishbone.Ack,
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WbErr_i => s_wishbone.Err,
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--+ local register if
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LocalWen_i => s_master_local_wen,
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LocalRen_i => s_master_local_ren,
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LocalAdress_i => s_master_local_adress,
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LocalData_i => s_master_local_din,
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LocalData_o => s_master_local_dout,
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LocalAck_o => s_master_local_ack,
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LocalError_o => s_master_local_error
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);
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WishBoneBusMonitorP : process is
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variable v_master_local_adress : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0);
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variable v_master_local_data : std_logic_vector(C_DATA_WIDTH-1 downto 0);
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variable v_valid_access : std_logic;
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begin
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wait until (s_master_local_wen = '1' or s_master_local_ren = '1') and rising_edge(s_wb_clk);
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v_master_local_adress := s_master_local_adress;
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v_master_local_data := s_master_local_din;
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v_valid_access := s_master_local_wen xor s_master_local_ren;
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wait until rising_edge(s_wb_clk);
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WB_CYC : assert v_valid_access = s_wishbone.Cyc
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report "ERROR: Wishbone cycle should be 0b" & to_string(v_valid_access) & " instead of 0b" & to_string(s_wishbone.Cyc)
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severity failure;
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if (v_valid_access = '1') then
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WB_ADDR : assert s_wishbone.Adr = v_master_local_adress
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report "ERROR: Wishbone address 0x" & to_hstring(s_wishbone.Adr) & " differ from local address 0x" & to_hstring(v_master_local_adress)
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severity failure;
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if (s_wishbone.We = '1') then
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WB_DATA : assert s_wishbone.WDat = v_master_local_data
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report "ERROR: Wishbone data 0x" & to_hstring(s_wishbone.WDat) & " differ from local data 0x" & to_hstring(v_master_local_data)
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severity failure;
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end if;
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end if;
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end process WishBoneBusMonitorP;
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i_WishBoneSlaveE : WishBoneSlaveE
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generic map (
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G_ADR_WIDTH => C_ADDRESS_WIDTH,
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G_DATA_WIDTH => C_DATA_WIDTH
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)
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port map (
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--+ wishbone system if
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WbRst_i => s_wb_reset,
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WbClk_i => s_wb_clk,
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--+ wishbone inputs
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WbCyc_i => s_wishbone.Cyc,
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WbStb_i => s_wishbone.Stb,
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WbWe_i => s_wishbone.We,
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WbAdr_i => s_wishbone.Adr,
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WbDat_i => s_wishbone.WDat,
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--* wishbone outputs
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WbDat_o => s_wishbone.RDat,
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WbAck_o => s_wishbone.Ack,
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WbErr_o => s_wishbone.Err,
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--+ local register if
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LocalWen_o => s_slave_local_wen,
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LocalRen_o => s_slave_local_ren,
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LocalAdress_o => s_slave_local_adress,
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LocalData_o => s_slave_local_dout,
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LocalData_i => s_slave_local_din
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);
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WbSlaveLocalP : process is
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variable v_register : t_register := (others => (others => '0'));
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begin
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wait until rising_edge(s_wb_clk);
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if (s_wb_reset = '1') then
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v_register := (others => (others => '0'));
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s_slave_local_din <= (others => '0');
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else
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if (s_slave_local_wen = '1') then
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v_register(slv_to_uint(s_slave_local_adress)) := s_slave_local_dout;
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elsif (s_slave_local_ren = '1') then
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s_slave_local_din <= v_register(slv_to_uint(s_slave_local_adress));
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end if;
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end if;
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end process WbSlaveLocalP;
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end architecture sim;
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