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55 lines
1.5 KiB
55 lines
1.5 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity WishBoneCheckerE is
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port (
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--+ wishbone system if
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WbRst_i : in std_logic;
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WbClk_i : in std_logic;
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--+ wishbone outputs
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WbMCyc_i : in std_logic;
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WbMStb_i : in std_logic;
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WbMWe_i : in std_logic;
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WbMAdr_i : in std_logic_vector;
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WbMDat_i : in std_logic_vector;
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--+ wishbone inputs
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WbSDat_i : in std_logic_vector;
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WbSAck_i : in std_logic;
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WbSErr_i : in std_logic
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);
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end entity WishBoneCheckerE;
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architecture check of WishBoneCheckerE is
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begin
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-- psl default clock is rising_edge(WbClk_i);
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--
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-- Wishbone protocol checks
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--
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-- psl property initialize(boolean init_state) is
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-- always ({WbRst_i} |=> {init_state[+] && {WbRst_i[*]; not(WbRst_i)}});
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--
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-- psl RULE_3_00 : assert initialize(not(WbMCyc_i) and not(WbMStb_i) and not(WbMWe_i))
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-- report "Wishbone rule 3.00 violated";
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--
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-- psl property reset_signal is
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-- always {not(WbRst_i); WbRst_i} |=> {(WbRst_i and not(WbClk_i))[*]; WbRst_i and WbClk_i};
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--
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-- psl RULE_3_05 : assert reset_signal
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-- report "Wishbone rule 3.05 violated";
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--
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-- -- psl property master_cycle_signal(boolean master_strobe, master_cyc) is
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-- -- always {master_strobe} |-> {master_cyc[+] && {not(master_strobe)[->]:WbClk_i}};
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-- --
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-- -- psl RULE_3_25 : assert master_cycle_signal(WbMStb_i, WbMCyc_i)
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-- -- report "Wishbone rule 3.25 violated";
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end architecture check;
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