library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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library libvhdl;
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use libvhdl.AssertP.all;
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entity StackT is
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end entity StackT;
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architecture sim of StackT is
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constant C_STACK_DEPTH : natural := 64;
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package SlvStack is new libvhdl.StackP
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generic map (
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STACK_TYPE => std_logic_vector(63 downto 0),
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MAX_LEN => C_STACK_DEPTH,
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to_string => to_hstring
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);
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shared variable sv_stack : SlvStack.t_stack;
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begin
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StackInitP : process is
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begin
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sv_stack.init(false);
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wait;
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end process StackInitP;
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StackTestP : process is
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variable v_data : std_logic_vector(63 downto 0);
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variable v_random : RandomPType;
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type t_scoreboard is array (natural range <>) of std_logic_vector(63 downto 0);
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variable v_scoreboard : t_scoreboard(0 to C_STACK_DEPTH-1);
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begin
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-- Check initial emptiness
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assert_true(sv_stack.is_empty, "Stack should be empty!");
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-- Fill stack
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v_random.InitSeed(v_random'instance_name);
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for i in 0 to C_STACK_DEPTH-1 loop
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v_data := v_random.RandSlv(64);
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v_scoreboard(i) := v_data;
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sv_stack.push(v_data);
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end loop;
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-- Check that it's full
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assert_true(sv_stack.is_full, "Stack should be full!");
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-- Check number of entries
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assert_equal(sv_stack.fillstate, C_STACK_DEPTH, "Stack should have" & integer'image(C_STACK_DEPTH) & "entries");
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-- Empty the stack
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for i in C_STACK_DEPTH-1 downto 0 loop
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sv_stack.pop(v_data);
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assert_equal(v_data, v_scoreboard(i));
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end loop;
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-- Check emptiness
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assert_true(sv_stack.is_empty, "Stack should be empty!");
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report "INFO: t_stack test finished successfully";
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wait;
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end process StackTestP;
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end architecture sim;
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