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144 lines
4.3 KiB
144 lines
4.3 KiB
-- ======================================================================
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-- UART Receiver
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-- Copyright (C) 2020 Torsten Meissner
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-------------------------------------------------------------------------
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-- This program is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 3 of the License, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with this program; if not, write to the Free Software Foundation,
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-- Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-- ======================================================================
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library libvhdl;
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use libvhdl.UtilsP.all;
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entity UartRx is
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generic (
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DATA_LENGTH : positive range 5 to 9 := 8;
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PARITY : boolean := true;
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CLK_DIV : natural := 10
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);
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port (
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reset_n_i : in std_logic; -- async reset
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clk_i : in std_logic; -- clock
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data_o : out std_logic_vector(DATA_LENGTH-1 downto 0); -- data output
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error_o : out std_logic; -- rx error
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valid_o : out std_logic; -- output data valid
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accept_i : in std_logic; -- output data accepted
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rx_i : in std_logic -- uart rx input
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);
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end entity UartRx;
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architecture rtl of UartRx is
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function to_integer (data : in boolean) return integer is
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begin
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if data then
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return 1;
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else
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return 0;
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end if;
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end function to_integer;
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type t_uart_state is (IDLE, RECEIVE, VALID);
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signal s_uart_state : t_uart_state;
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signal s_data : std_logic_vector(DATA_LENGTH+1+to_integer(PARITY) downto 0);
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signal s_clk_en : boolean;
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begin
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ClkDivP : process (clk_i, reset_n_i) is
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variable v_clk_cnt : natural range 0 to CLK_DIV-1;
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begin
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if (reset_n_i = '0') then
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s_clk_en <= false;
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v_clk_cnt := CLK_DIV-1;
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elsif (rising_edge(clk_i)) then
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s_clk_en <= false;
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if (s_uart_state = IDLE) then
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v_clk_cnt := CLK_DIV-2;
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elsif (s_uart_state = RECEIVE) then
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if (v_clk_cnt = 0) then
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v_clk_cnt := CLK_DIV-1;
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else
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v_clk_cnt := v_clk_cnt - 1;
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end if;
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if (v_clk_cnt = CLK_DIV/2-1) then
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s_clk_en <= true;
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end if;
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end if;
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end if;
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end process ClkDivP;
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RxP : process (clk_i, reset_n_i) is
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variable v_bit_cnt : natural range 0 to s_data'length-1;
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begin
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if (reset_n_i = '0') then
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s_uart_state <= IDLE;
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s_data <= (others => '0');
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valid_o <= '0';
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v_bit_cnt := 0;
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elsif (rising_edge(clk_i)) then
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FsmL : case s_uart_state is
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when IDLE =>
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valid_o <= '0';
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v_bit_cnt := s_data'length-1;
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if (rx_i = '0') then
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s_uart_state <= RECEIVE;
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end if;
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when RECEIVE =>
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if (s_clk_en) then
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s_data <= rx_i & s_data(s_data'length-1 downto 1);
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if (v_bit_cnt = 0) then
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valid_o <= '1';
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s_uart_state <= VALID;
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else
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v_bit_cnt := v_bit_cnt - 1;
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end if;
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end if;
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when VALID =>
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valid_o <= '1';
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if (valid_o = '1' and accept_i = '1') then
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valid_o <= '0';
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s_uart_state <= IDLE;
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end if;
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end case;
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end if;
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end process RxP;
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ParityG : if PARITY generate
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data_o <= s_data(s_data'length-3 downto 1);
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error_o <= '1' when odd_parity(s_data(s_data'length-3 downto 1)) /= s_data(s_data'length-2) or
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s_data(s_data'length-1) = '0' else
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'0';
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else generate
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data_o <= s_data(s_data'length-2 downto 1);
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error_o <= '1' when s_data(s_data'length-1) = '0' else '0';
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end generate ParityG;
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end architecture rtl;
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