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84 lines
2.3 KiB
84 lines
2.3 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity QueueT is
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end entity QueueT;
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architecture sim of QueueT is
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shared variable sv_simple_queue : work.QueueP.t_simple_queue;
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shared variable sv_list_queue : work.QueueP.t_list_queue;
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begin
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SimpleQueueTestP : process is
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variable v_data : std_logic_vector(63 downto 0);
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begin
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-- check initial emptiness
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assert sv_simple_queue.is_empty
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report "ERROR: queue should be empty!"
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severity failure;
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for i in 0 to 63 loop
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sv_simple_queue.push(std_logic_vector(to_unsigned(i, 64)));
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end loop;
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-- check that it's full
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assert sv_simple_queue.is_full
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report "ERROR: queue should be full!"
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severity failure;
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-- empty the queue
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for i in 0 to 63 loop
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sv_simple_queue.pop(v_data);
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assert v_data = std_logic_vector(to_unsigned(i, 64))
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report "ERROR: read data should be " & integer'image(i) &
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" instead of " & integer'image(to_integer(unsigned(v_data)))
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severity failure;
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end loop;
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-- check emptiness
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assert sv_simple_queue.is_empty
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report "ERROR: queue should be empty!"
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severity failure;
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report "INFO: t_simple_queue test finished successfully";
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wait;
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end process SimpleQueueTestP;
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ListQueueTestP : process is
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variable v_data : std_logic_vector(63 downto 0);
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begin
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-- check initial emptiness
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assert sv_list_queue.is_empty
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report "ERROR: queue should be empty!"
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severity failure;
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for i in 0 to 63 loop
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sv_list_queue.push(std_logic_vector(to_unsigned(i, 64)));
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end loop;
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-- check that it's full
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assert sv_list_queue.is_full
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report "ERROR: queue should be full!"
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severity failure;
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-- empty the queue
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for i in 0 to 63 loop
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sv_list_queue.pop(v_data);
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assert v_data = std_logic_vector(to_unsigned(i, 64))
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report "ERROR: read data should be " & integer'image(i) &
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" instead of " & integer'image(to_integer(unsigned(v_data)))
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severity failure;
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end loop;
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-- check emptiness
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assert sv_list_queue.is_empty
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report "ERROR: queue should be empty!"
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severity failure;
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report "INFO: t_list_queue test finished successfully";
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wait;
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end process ListQueueTestP;
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end architecture sim;
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