|
@@ -0,0 +1,104 @@
|
|
1
|
+#include <avr/io.h>
|
|
2
|
+#include <avr/interrupt.h>
|
|
3
|
+#include <avr/sleep.h>
|
|
4
|
+#include <stdint.h>
|
|
5
|
+#define F_CPU 9600000UL
|
|
6
|
+
|
|
7
|
+volatile uint8_t beep_disable = 0;
|
|
8
|
+volatile uint8_t beep_enable = 0;
|
|
9
|
+
|
|
10
|
+static void set_wait_timer (void);
|
|
11
|
+void set_beep_timer (uint8_t outport);
|
|
12
|
+
|
|
13
|
+
|
|
14
|
+// main function
|
|
15
|
+int main (void)
|
|
16
|
+{
|
|
17
|
+
|
|
18
|
+ DDRB = (1<<DDB1) | (1<<DDB0); // set PB0 & PB1 to output
|
|
19
|
+
|
|
20
|
+ set_sleep_mode(SLEEP_MODE_IDLE); // set sleep mode
|
|
21
|
+
|
|
22
|
+ set_beep_timer(0); // generate signal with beeper frequency
|
|
23
|
+
|
|
24
|
+ while (beep_disable == 0) {} // wait for expired beep counter
|
|
25
|
+
|
|
26
|
+ set_wait_timer(); // start timer to wait 600 secs
|
|
27
|
+
|
|
28
|
+ // wait for expired wait counter
|
|
29
|
+ while (beep_enable == 0) {
|
|
30
|
+ sleep_mode(); // goto sleep until next interrupt
|
|
31
|
+ }
|
|
32
|
+
|
|
33
|
+ // endless loop until switch-off
|
|
34
|
+ while(1) {
|
|
35
|
+ set_beep_timer(0); // generate signal with beeper frequency
|
|
36
|
+ while (beep_disable == 0) {}
|
|
37
|
+ set_beep_timer(1); // generate signal with beeper frequency
|
|
38
|
+ while (beep_disable == 0) {}
|
|
39
|
+ }
|
|
40
|
+
|
|
41
|
+ return 0;
|
|
42
|
+}
|
|
43
|
+
|
|
44
|
+
|
|
45
|
+// routine to set timer0 for waiting until beep
|
|
46
|
+static void set_wait_timer (void)
|
|
47
|
+{
|
|
48
|
+ cli();
|
|
49
|
+ TCCR0A = 0x00; // set timer0 to normal mode
|
|
50
|
+ TCCR0B = (1<<CS02) | (1<<CS00); // set timer0 prescaler to 1024
|
|
51
|
+ TIMSK0 = (1<<TOIE0); // interrupt enable for timer0 overflow
|
|
52
|
+ sei();
|
|
53
|
+ return;
|
|
54
|
+}
|
|
55
|
+
|
|
56
|
+
|
|
57
|
+// routine to set timer0 for to generate frequency for beeper
|
|
58
|
+void set_beep_timer (uint8_t outport)
|
|
59
|
+{
|
|
60
|
+ cli();
|
|
61
|
+ if (outport == 0) {
|
|
62
|
+ TCCR0A = (1<<COM0A0) | (1<<WGM01); // toggle OC0A on compare match , ctc mode
|
|
63
|
+ } else {
|
|
64
|
+ TCCR0A = (1<<COM0B0) | (1<<WGM01); // toggle OC0B on compare match , ctc mode
|
|
65
|
+ }
|
|
66
|
+ TCCR0B = (1<<CS00); // set timer0 prescaler to 1 (no prescaling)
|
|
67
|
+ OCR0A = 0xE7; // set output compare register a
|
|
68
|
+ TIMSK0 = (1<<OCIE0A); // interrupt enable for timer0 compare match a
|
|
69
|
+ sei();
|
|
70
|
+ return;
|
|
71
|
+}
|
|
72
|
+
|
|
73
|
+
|
|
74
|
+// interrupt routine for timer0 output compare match a
|
|
75
|
+ISR(TIM0_COMPA_vect)
|
|
76
|
+{
|
|
77
|
+ static uint16_t overflow = 0;
|
|
78
|
+ // after count up to 1 second
|
|
79
|
+ // deactivate beeper & disable timer0 output compare match a interrupt
|
|
80
|
+ if (overflow <= 10920) {
|
|
81
|
+ beep_disable = 0;
|
|
82
|
+ overflow ++;
|
|
83
|
+ } else {
|
|
84
|
+ TIMSK0 &= ~(1<<OCIE0A); // interrupt disable for timer0 compare match a
|
|
85
|
+ beep_disable = 1;
|
|
86
|
+ overflow = 0;
|
|
87
|
+ }
|
|
88
|
+}
|
|
89
|
+
|
|
90
|
+
|
|
91
|
+// interrupt routine for timer0 overflow
|
|
92
|
+ISR(TIM0_OVF_vect)
|
|
93
|
+{
|
|
94
|
+ static uint16_t overflow = 0;
|
|
95
|
+ // after count up to 1200 seconds
|
|
96
|
+ // activate beeper & disable timer0 overflow interrupt
|
|
97
|
+ if (overflow <= 6000) { // for test: 30 ca. 6 sek.
|
|
98
|
+ overflow ++;
|
|
99
|
+ } else {
|
|
100
|
+ beep_enable = 1;
|
|
101
|
+ TIMSK0 &= ~(1<<TOIE0); // interrupt disable for timer0 overflow
|
|
102
|
+ }
|
|
103
|
+}
|
|
104
|
+
|