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changed spi ports sclk, miso & mosi to inout, so we can remove the internal helper signals

T. Meissner 5 years ago
parent
commit
6cd9accd03
1 changed files with 12 additions and 14 deletions
  1. 12
    14
      raspiFpga/src/RaspiFpgaE.vhd

+ 12
- 14
raspiFpga/src/RaspiFpgaE.vhd View File

@@ -10,10 +10,10 @@ library machxo2;
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 entity RaspiFpgaE is
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   port (
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     --+ SPI slave if
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-    SpiSclk_i    : in  std_logic;
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-    SpiSte_i     : in  std_logic;
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-    SpiMosi_i    : in  std_logic;
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-    SpiMiso_o    : out std_logic;
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+    SpiSclk_i    : inout std_logic;
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+    SpiSte_i     : in    std_logic;
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+    SpiMosi_i    : inout std_logic;
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+    SpiMiso_o    : inout std_logic;
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     --* interrupt line to raspi
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     RaspiIrq_o   : out std_logic
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   );
@@ -104,7 +104,7 @@ architecture rtl of RaspiFpgaE is
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   component OSCH is
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     -- synthesis translate_off
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     generic (
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-      NOM_FREQ : string := "2.56"
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+      NOM_FREQ : string := "26.60"
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     );
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     -- synthesis translate_on
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     port (
@@ -160,7 +160,7 @@ begin
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     generic map (
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       NOM_FREQ => "26.60"
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     )
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-    -- syntheses on
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+    -- synthesis on
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     port map (
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       STDBY    => '0',
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       OSC      => s_sys_clk,
@@ -186,10 +186,6 @@ begin
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   end process ResetP;
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-  s_spi_sclk <= SpiSclk_i;
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-  s_spi_miso <= SpiSte_i;
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-  s_spi_mosi <= SpiMosi_i;
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-
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   --+ EFB SPI slave instance
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   i_EfbSpiSlave : EfbSpiSlave
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     port map (
@@ -202,9 +198,9 @@ begin
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       wb_dat_i => s_wb_master_dat,
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       wb_dat_o => s_wb_slave_dat,
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       wb_ack_o => s_wb_ack,
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-      spi_clk  => s_spi_sclk,
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-      spi_miso => s_spi_miso,
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-      spi_mosi => s_spi_mosi,
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+      spi_clk  => SpiSclk_i,
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+      spi_miso => SpiMiso_o,
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+      spi_mosi => SpiMosi_i,
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       spi_scsn => SpiSte_i,
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       spi_irq  => s_efb_irq
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     );
@@ -228,7 +224,7 @@ begin
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       --+ wishbone inputs
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       WbDat_i       => s_wb_slave_dat,
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       WbAck_i       => s_wb_ack,
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-      WbErr_i       => open,
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+      WbErr_i       => '0',
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       --+ local register if
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       LocalWen_i    => s_local_wen,
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       LocalRen_i    => s_local_ren,
@@ -262,4 +258,6 @@ begin
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     );
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+  RaspiIrq_o <= '0';
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+
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 end architecture rtl;